Technical Reports
Communication SW Generation from TL to PCA Level for MPSoC
Ines Viskic, Samar Abdi, Daniel Gajski, "Communication SW Generation from TL to PCA Level for MPSoC", TR 07-07, July 2007 download pdf
Design of a MP3 Decoder using the System-On-Chip Environment (SCE)
Andreas Gerstlauer, Dongwan Shin, Samar Abdi, Pramod Chandraiah, Daniel Gajski, "Design of a MP3 Decoder using the System-On-Chip Environment (SCE)", TR 07-05, November 2, 2007 download pdf
System-Level Modeling and Simulation of an Elevator Control System
Daniel Castellanos, Rainer Doemer, "System-Level Modeling and Simulation of an Elevator Control System", TR 07-04, June 25, 2007 download pdf
A Simplified Java Compilation System for Resource-Constrained Embedded Processors
Carmen Badea, Alexandru Nicolau, Alexander Veidenbaum, "A Simplified Java Compilation System for Resource-Constrained Embedded Processors", TR 07-03, June 2007. Complete TR is available upon request
Iterative System Tuning for Proactive Systems by Formal Verification and System Prototype: System Prototype Program Interface
Minyoung Kim, Mark-Oliver Stehr, Carolyn Talcott, Kyoungwoo Lee, Nikil Dutt, Nalini Venkatasubramanian, "Iterative System Tuning for Proactive Systems by Formal Verification and System Prototype: System Prototype Program Interface", TR 07-02, January 2007. Complete TR is available upon request
Transaction Level Platform Modeling in SystemC for Multi-Processor Designs
Lochi Yu, Samar Abdi, Daniel Gajski, "Transaction Level Platform Modeling in SystemC for Multi-Processor Designs", TR 07-01 January 2007 download pdf
Transaction Level Platform Modeling in SystemC for Multi-Processor Designs
Lochi Yu, Samar Abdi, Daniel Gajski, “Transaction Level Platform Modeling in SystemC for Multi-Processor Designs,”TR 06-15, January 2007. download pdf
Efficient Debugging and Tracing of System Level Designs
E. Johnson, A. Gerstlauer, R. Doemer, “Efficient Debugging and Tracing of System Level Designs,” TR 06-08, May 2006. download pdf/span>
UBC: A Universal Bus Channel for Transaction level Modeling
S. Abdi, D. Gajski, “UBC: A Universal Bus Channel for Transaction level Modeling,” TR 06-07, April 2006. Complete TR is available upon request.
Modeling, Simulation and Synthesis in anEmbedded Software Design Flow for an ARM Processor
G. Schirner, G. Sachdeva, A. Gerstalauer, R. Doemer, “Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor,”TR 06-06, April 2006. download pdf
NISC Double-Handshake Communication Interface
B. Gorjiara, M. Reshadi, D. Gajski, “NISC Double-Handshake Communication Interface,” TR 06-05, March 2006. download pdf
Processor Customization on a Xilinx Multimedia Board
P. Biswas, S. Banerjee, and N. Dutt, “Processor Customization on a Xilinx Multimedia Board,” TR 06-04, March 2006. download pdf
A Framework for Memory and Communication Architecture Co-synthesis in MPSoCs
S. Pasricha and N. Dutt, “A Framework for Memory and Communication Architecture Co-synthesis in MPSoCs,”TR 06-03, February 2006. download pdf
Using Annotations to Facilitate Power vs Quality Trade-offs in Streaming Applications
R. Cornea, A. Nicolau, N. Dutt, “Using Annotations to Facilitate Power vs Quality Trade-offs in Streaming Applications,” TR 06-02, March 2006. download pdf
Necessary and Sufficient Functionality and Parameters for SoC Communication
A. Gerstlauer, G. Schirner, D. Shin, and J. Peng, “Necessary and Sufficient Functionality and Parameters for SoC Communication,” TR 06-01, May 2006. Complete TR is available upon request.
Selecting Granularity of Parallelism for Tasks executing on Dynamically Reconfigurable Architectures
S. Banerjee, E. Bozorgzadeh, N. Dutt, “Selecting Granularity of Parallelism for Tasks executing on Dynamically Reconfigurable Architectures,” TR 06-14, December 2006. download pdf
Content-aware Power Optimizations for Multimedia Streaming Over Wireless Networks
R. Cornea, A. Nicolau, N. Dutt, “Content-aware Power Optimizations for Multimedia Streaming Over Wireless Networks ,” TR 06-13, November 2006. Complete TR is available upon request.
Power-Performance Trade-Offs in On-Chip Communication Architecture Synthesis using the CAPPS Framework
S. Pasricha, Y. Park, F. Kurdahi, N. Dutt , “Power-Performance Trade-Offs in On-Chip Communication Architecture Synthesis using the CAPPS Framework,” TR 06-12, November 2006. download pdf
Transaction Level Modeling of Computation
R. Doemer, “Transaction Level Modeling of Computation,” TR 06-11, August 2006. download pdf
System-On-Chip Component Models
A. Gerstlauer, G. Schirner, D. Shin, J. Peng, R. Doemer, D. Gajski, “System-On-Chip Component Models,” TR 06-10, May 2006. Complete TR is available upon request.
Stream Annotations for Energy Trade-offs in a VideoDecoder for Multimedia Applications
R. Cornea, A. Nicolau, N. Dutt, “Stream Annotations for Energy Trade-offs in a Video Decoder for Multimedia Applications,”TR 06-09, May 2006. download pdf
Communication Design for No Instruction Set Computer
D. Gajski, and J. Trajkovic, "Communication Design for No Instruction Set Computer," TR 05-09, July 2005. download pdf
General Transducer Architecture
D. Gajski, H. Cho, and S. Abdi, " General Transducer Architecture," TR 05-08, August 2005. download pdf
Equivalence Checking of Arithmetic Expressions Using Fast Evaluation
M. Ghodrat, and T. Givargis, "Equivalence Checking of Arithmetic Expressions Using Fast Evaluation," TR 05-07, July 2005. download pdf
Expression Equivalence Checking using Interval Analysis
M. Ghodrat, and T. Givargis, "Expression Equivalence Checking using Interval Analysis," TR 05-06, May 2005. download pdf
Using Result Oriented Modeling for Fast yet Accurate TLMs,
G Schirner and R. Doemer, "Using Result Oriented Modeling for Fast yet Accurate TLMs," TR 05-05, May 2005. download pdf
Specification and Design of an MP3 Audio Decoder
P. Chandriaiah, and R. Doemer, "Specification and Design of an MP3 Audio Decoder," TR 05-04, May 2005. download pdf
System Level Modeling of an AMBA Bus
G. Schirner and R. Doemer, "System Level Modeling of an AMBA Bus, " TR 05-03, April 2005. download pdf
HW-SW Partitioning for architectures with Partial Dynamic Reconfiguration
S. Banerjee, E. Bozorgzadeh, and N. Dutt, "HW-SW Partitioning for architectures with Partial Dynamic Reconfiguration," TR 05-02, April 2005. download pdf
PBPAIR: Probability Based Power Aware Intra Refresh, A New Energy-efficient Error-resilient Encoding Scheme
M. Kim, H. Oh, N. Dutt, A. Nicolau, and N. Venkatasubramanian, "PBPAIR: Probability Based Power Aware Intra Refresh, A New Energy-efficient Error-resilient Encoding Scheme," TR 05-01, February 2005. download pdf
NISC Technology Online Toolset
M. Reshadi, B. Gorjiara, D. Gajski, "NISC Technology Online Toolset," TR 05-19, December 2005. download pdf
TR 05-18 cancelled
TR 05-17 cancelled
Software Virtual Memory Management for MMU-Less Embedded Systems
S. Choudhuri and T. Givargis, "Software Virtual Memory Management for MMU-Less Embedded Systems," TR 05-16, November 2005. download pdf
A Tool for Functional Verfication of System Level Model Refinements
S. Abdi and D. Gajski, "A Tool for Functional Verfication of System Level Model Refinements," TR 05-15, October 2005. download pdf
Bus Matrix Communication Architecture Synthesis
S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Bus Matrix Communication Architecture Synthesis," TR 05-13, October 2005. download pdf
System Modeling: A Case Study on A Wireless Sensor Network
G. Sachdeva, R.Doemer, and P. Chou, "System Modeling: A Case Study on A Wireless Sensor Network," TR 05-12, June 2005. download pdf
NISC Technology and Preliminary Results
M. Reshadi, B. Gorjiara, and D. Gajski, "NISC Technology and Preliminary Results," TR 05-11, August 2005. download pdf
TL Environment
D.Gajski, A. Gerstlauer, R. Doemer, S. Abdi, J. Peng, D. Shin, "TL Environment," TR 05-10, July 2005. download pdf
Systematic Power Management of Heterogeneous Real-time Systems by Dynamic Schedule Analysis
B. Gorjiara and N. Bagherzadeh, "Systematic Power Management of Heterogeneous Real-time Systems by Dynamic Schedule Analysis," TR 04-26, August 2004. download pdf
Procrastination Scheduling in Fixed Priority Real-Time Systems
R. Jejurikar and R. Gupta, "Procrastination Scheduling in Fixed Priority Real-Time Systems," TR 04-09, April, 2004. download pdf
System-on-Chip Communication Modeling Style Guide
D. Shin, A. Gerstlauer, R. Doemer, D. Gajski, "System-on-Chip Communication Modeling Style Guide," TR 04-25, July 2004. download pdf