Technical Reports

Daniel Castellanos, Rainer Doemer, "System-Level Modeling and Simulation of an Elevator Control System", TR 07-04, June 25, 2007 download pdf

Carmen Badea, Alexandru Nicolau, Alexander Veidenbaum, "A Simplified Java Compilation System for Resource-Constrained Embedded Processors", TR 07-03, June 2007. Complete TR is available upon request

Minyoung Kim, Mark-Oliver Stehr, Carolyn Talcott, Kyoungwoo Lee, Nikil Dutt, Nalini Venkatasubramanian, "Iterative System Tuning for Proactive Systems by Formal Verification and System Prototype: System Prototype Program Interface", TR 07-02, January 2007. Complete TR is available upon request

Lochi Yu, Samar Abdi, Daniel Gajski, "Transaction Level Platform Modeling in SystemC for Multi-Processor Designs", TR 07-01 January 2007 download pdf

Lochi Yu, Samar Abdi, Daniel Gajski, “Transaction Level Platform Modeling in SystemC for Multi-Processor Designs,”TR 06-15, January 2007. download pdf

R. Cornea, A. Nicolau, N. Dutt, “Using Annotations to Facilitate Power vs Quality Trade-offs in Streaming Applications,” TR 06-02, March 2006. download pdf

A. Gerstlauer, G. Schirner, D. Shin, and J. Peng, “Necessary and Sufficient Functionality and Parameters for SoC Communication,” TR 06-01, May 2006. Complete TR is available upon request.  

S. Banerjee, E. Bozorgzadeh, N. Dutt, “Selecting Granularity of Parallelism for Tasks executing on Dynamically Reconfigurable Architectures,” TR 06-14, December 2006. download pdf

R. Cornea, A. Nicolau, N. Dutt, “Content-aware Power Optimizations for Multimedia Streaming Over Wireless Networks ,” TR 06-13, November 2006. Complete TR is available upon request.

S. Pasricha, Y. Park, F. Kurdahi, N. Dutt , “Power-Performance Trade-Offs in On-Chip Communication Architecture Synthesis using the CAPPS Framework,” TR 06-12, November 2006. download pdf

R. Doemer, “Transaction Level Modeling of Computation,” TR 06-11, August 2006. download pdf

A. Gerstlauer, G. Schirner, D. Shin, J. Peng, R. Doemer, D. Gajski, “System-On-Chip Component Models,” TR 06-10, May 2006. Complete TR is available upon request.

R. Cornea, A. Nicolau, N. Dutt, “Stream Annotations for Energy Trade-offs in a Video Decoder for Multimedia Applications,”TR 06-09, May 2006. download pdf

E. Johnson, A. Gerstlauer, R. Doemer, “Efficient Debugging and Tracing of System Level Designs,” TR 06-08, May 2006. download pdf/span>

S. Abdi, D. Gajski, “UBC: A Universal Bus Channel for Transaction level Modeling,” TR 06-07, April 2006. Complete TR is available upon request.  

G. Schirner, G. Sachdeva, A. Gerstalauer, R. Doemer, “Modeling, Simulation and Synthesis in an Embedded Software Design Flow for an ARM Processor,”TR 06-06, April 2006. download pdf

B. Gorjiara, M. Reshadi, D. Gajski, “NISC Double-Handshake Communication Interface,” TR 06-05, March 2006. download pdf

P. Biswas, S. Banerjee, and N. Dutt, “Processor Customization on a Xilinx Multimedia Board,” TR 06-04, March 2006. download pdf

S. Pasricha and N. Dutt, “A Framework for Memory and Communication Architecture Co-synthesis in MPSoCs,”TR 06-03, February 2006. download pdf

G. Schirner and R. Doemer, "System Level Modeling of an AMBA Bus, " TR 05-03, April 2005. download pdf

S. Banerjee, E. Bozorgzadeh, and N. Dutt, "HW-SW Partitioning for architectures with Partial Dynamic Reconfiguration," TR 05-02, April 2005. download pdf

M. Kim, H. Oh, N. Dutt, A. Nicolau, and N. Venkatasubramanian, "PBPAIR: Probability Based Power Aware Intra Refresh, A New Energy-efficient Error-resilient Encoding Scheme," TR 05-01, February 2005. download pdf

M. Reshadi, B. Gorjiara, D. Gajski, "NISC Technology Online Toolset," TR 05-19, December 2005. download pdf

TR 05-18 cancelled

TR 05-17 cancelled

S. Choudhuri and T. Givargis, "Software Virtual Memory Management for MMU-Less Embedded Systems," TR 05-16, November 2005. download pdf

S. Abdi and D. Gajski, "A Tool for Functional Verfication of System Level Model Refinements," TR 05-15, October 2005. download pdf

S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Bus Matrix Communication Architecture Synthesis," TR 05-13, October 2005. download pdf

G. Sachdeva, R.Doemer, and P. Chou, "System Modeling: A Case Study on A Wireless Sensor Network," TR 05-12, June 2005. download pdf

M. Reshadi, B. Gorjiara, and D. Gajski, "NISC Technology and Preliminary Results," TR 05-11, August 2005. download pdf

D.Gajski, A. Gerstlauer, R. Doemer, S. Abdi, J. Peng, D. Shin, "TL Environment," TR 05-10, July 2005. download pdf

D. Gajski, and J. Trajkovic, "Communication Design for No Instruction Set Computer," TR 05-09, July 2005. download pdf

D. Gajski, H. Cho, and S. Abdi, " General Transducer Architecture," TR 05-08, August 2005. download pdf

M. Ghodrat, and T. Givargis, "Equivalence Checking of Arithmetic Expressions Using Fast Evaluation," TR 05-07, July 2005. download pdf

M. Ghodrat, and T. Givargis, "Expression Equivalence Checking using Interval Analysis," TR 05-06, May 2005. download pdf

G Schirner and R. Doemer, "Using Result Oriented Modeling for Fast yet Accurate TLMs," TR 05-05, May 2005. download pdf

P. Chandriaiah, and R. Doemer, "Specification and Design of an MP3 Audio Decoder," TR 05-04, May 2005. download pdf

R. Doemer, A. Gerstlauer, D. Shin, "Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components," TR 04-19, July 22, 2004. download pdf

R. Jejurikar and R. Gupta, "Integrating Processor Slowdown and Preemption Threshold Scheduling for Energy Efficiency in Real Time Embedded Systems," TR 04-03, February 16, 2004. download pdf

S. Banerjee and N. Dutt, "Very Fast Simulated Annealing for HW-SW Partitioning," TR 04-18, June 2004. download pdf

J. Trajkovic and A. Veidenbaum, "Reducing SDRAM Energy Consumption in Embedded Systems," TR 04-02, October 2004. download pdf

P. Chandraiah, H. Schirner, N. Srinivas, and R. Doemer, "System-On Chip Modeling and Design: A Case Study on MP3 Decoder," TR 04-17, June 21, 2004. download pdf