Technical Reports
Computing Static Slowdown Factors under EDF Scheduling when Deadline less than Period
R. Jejurikar, R. Gupta, “Computing Static Slowdown Factors under EDF Scheduling when Deadline less than Period,” TR 02-36, December 13, 2002. download pdf
Interactive System Design Flow
J. Peng, L. Cai, A. Gerstlauer, D. D. Gajski, “Interactive System Design Flow,” TR 02-15, April 15, 2002. download pdf
Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis
S. Gupta, N. Dutt, R. Gupta, A. Nicolau, “Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis,” TR 02-35, December 2002. download pdf
Automatic Model Refinement for Fast Architecture Exploration
J. Peng, S. Abdi, D. D. Gajski, “Automatic Model Refinement for Fast Architecture Exploration,” TR 02-14, April 1, 2002. download pdf
Mapping Loops on Coarse-Grain Reconfigurable Architectures Using Memory Operation Sharing
J. Leei, K. Choi, N. Dutt, “Mapping Loops on Coarse-Grain Reconfigurable Architectures Using Memory Operation Sharing," TR 02-34, September 2002. download pdf
Interface Synthesis from Protocol Specification
D. Shin, D. D. Gajski, “Interface Synthesis from Protocol Specification,” TR 02-13, April 12, 2002. download pdf
System-Level Design Flow: What is needed and what is not
D. D. Gajski, “System-Level Design Flow: What is needed and what is not," TR 02-33, November 26, 2002. download pdf
Queue Generation Algorithm for Interface Synthesis
D. Shin, D. D. Gajski, “Queue Generation Algorithm for Interface Synthesis,” TR 02-12, April 11, 2002. download pdf
Variable Mapping of System Level Design
D. D. Gajski, L. Cai, “Variable Mapping of System Level Design," TR 02-32, October 8, 2002. download pdf
Scheduling in RTL Design Methodology
D. Shin, D. D. Gajski, “Scheduling in RTL Design Methodology,” TR 02-11, April 12, 2002. download pdf
Grouping-Based Architecture Exploration of System-Level Design
D. D. Gajski, L. Cai, “Grouping-Based Architecture Exploration of System-Level Design," TR 02-31, August 16, 2002. download pdf
Optimal Indexing for Cache Miss Reduction in Embedded Systems
T. Givargis, “Optimal Indexing for Cache Miss Reduction in Embedded Systems,” TR 02-10, July 4, 2002. download pdf
Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis
S. Gupta, N. Savoiu, N. Dutt, R. Gupta, A. Nicolau, “Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis," TR 02-29, October 1, 2002. download pdf
RTL Design and Synthesis of Sequential Matrix Multiplication
P. Zhang, D. D. Gajski, “RTL Design and Synthesis of Sequential Matrix Multiplication,” TR 02-09, April 3, 2002. download pdf
SCE Environment – Tutorial
S. Abdi, J. Peng, R. Doemer, D. Shin, A. Gerstlauer, A. Gluhak, L. Cai, Q. Xie, H. Yu, P. Zhang, D. D. Gajski, “SCE Environment – Tutorial," TR 02-28, September 24, 2002. download pdf
System Level Design Using SpecC Profiler
L. Cai, D. D. Gajski, “System Level Design Using SpecC Profiler,” TR 02-08, April 1, 2002. download pdf
Automatic Instruction Set Design Through Efficient Instruction Encoding for Application-Specific Processors
J. Lee, K. Choi, N. Dutt, “Automatic Instruction Set Design Through Efficient Instruction Encoding for Application-Specific Processors,” TR 02-23, August 8, 2002. download pdf
Introduction of Design-Oriented Profiler of SpecC Language
L. Cai,D. D. Gajski, “Introduction of Design-Oriented Profiler of SpecC Language,” TR 02-07, March 1, 2002. download pdf
Optimal Cache Organization using an Allocation Tree
T. Givargis, “Optimal Cache Organization using an Allocation Tree,” TR 02-22, September 11, 2002. download pdf
Parity Checker Implementations in SpecC
Q. Xie, D. D. Gajski, "Parity Checker Implementations in SpecC,” TR 02-06, January 27, 2002. download pdf
Energy Aware Task Scheduling with Task Synchronization for Embedded Real Time Systems
R. Jejurikar, R. Gupta, “Energy Aware Task Scheduling with Task Synchronization for Embedded Real Time Systems,” TR 02-21, June 21, 2002. download pdf
Datapath Synthesis for a 16-Bit Microprocessor
H. Yu, D. D. Gajski, “Datapath Synthesis for a 16-Bit Microprocessor,” TR 02-05, January 22, 2002. download pdf
Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV
P. Mishra, N. Dutt, “Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV,” TR 02-26, September 13, 2002. download pdf
Specification Tuning of System-Level Design
L. Cai and D Gajski, "Specification Tuning of System-Level Design,” TR 02-20, June 6, 2002. download pdf
The Formal Execution Semantics of SpecC
W. Mueller, R. Doemer, A. Gerstlauer, “The Formal Execution Semantics of SpecC,” TR 02-04, January 11, 2002. download pdf