Fadi Kurdahi

Contact Information

VLSI system design, design automation of digital systems
(949) 824-8104

CECS Director

Fadi Kurdahi is the Director of CECS and and a Research Professor at University of California, Irvine.

Professor Kurdahi’s Research

Professor Kurdahi’s research interests include:

  • Early estimation and exploration in hardware/software co-design of embedded systems
  • Design methodology of large scale systems
  • Low-power, process-aware Systems-on-Chip design
  • Mobile and portable wireless and multimedia systems
  • Reconfigurable computing
  • Software-defined Radio

Current Research

Mobile Collaborative Video

The emergence of pico projectors as a part of future mobile devices presents unique opportunities for collaborative settings, especially in entertainment applications, such as video playback. By aggregating pico projectors from several users, it is possible to enhance resolution, brightness, or frame rate. In this paper we present a camera-based methodology for the alignment and synchronization of multiple projectors. The approach does not require any complicated ad hoc network setup among the mobile devices. A prototype system has been set up and used to test the proposed techniques.

Wireless Systems Cognitive Power Management

Our objective is to use new cognitive power management techniques for memory dominated mobile devices that exploit the variable nature of the wireless channel. The approach is based on the novel concept of Dynamic Margin Scaling which redefines architectural error tolerance of memory blocks based on the time varying tolerance of the application to hardware induced errors. Thus, the margin of acceptable performance can be dynamically managed by the needs of the application utilizing the hardware unit at that instant in time. Specifically, in the case of wireless systems, we exploit the slack in the received signal to noise ratio (SNR) to accordingly change the hardware noise at run time through aggressive voltage scaling. Depending on the scenario at hand, this approach leads to reducing power consumption by 20-40%, while maintaining the required quality of service (QoS). The proposed approach enables designers to abstract the concepts of power efficiency and error awareness for memory dominated devices early in the design cycle, with significant implications on the cost, performance and reliability attributes of the overall structure.

Resilient multimedia coding

Today, video accounts for a significant portion of data transferred over the internet, reaching over 50% in the near future. One of the fastest growing sub-segments of this traffic is video over mobile devices. Unfortunately, battery technology is lagging behind in capacity, limiting the amount of time users can spend watching videos over their phones or tablets. The power consumption of these devices can be reduced by voltage scaling, but up to a limit. This project explores the possibility of significant power saving through extreme measures which take advantage of the inherent resilience of multimedia applications

Error-aware circuits, architectures, modeling and design tradeoffs

In this project we investigate the effect of voltage over scaling on the embedded memories functionality. Then we propose fault tolerant adaptive voltage scaling and adaptive body biasing as a mean of reducing power consumption in embedded memories such as processor caches and other data and scratchpad memories. These techniques tradeoff_ reliability versus power savings as a function of the time varying quality of the incoming data, as long as the signal to noise ratio at the decision device is maintained at a desirable level. Moreover, we address the notion of error-awareness across different abstraction layers physical, application, network, and technology for the next generation SoCs. We show that utilizing proposed techniques on embedded memories (mainly through aggressive voltage scaling) will result in a)appreciable power reduction in wireless systems depending on the application, b) savings in cost and area by reducing or eliminating the need for circuit redundancy, and c) achieving a higher effective yield” by tolerating errors at the system or architecture level level while keeping other parameters constant.

Architectural Support for Distributed Event-Based Runtime Verification

This project introduces a distributed automata-based runtime verification (RV) architecture for specifications in a highly expressive _first order linear temporal logic of events (FOLTLe) applied to multi-many cores and networks on chip, to address the substantial performance and power overhead of pure software RV frameworks.

Thermal and power-aware Chip design

This project focuses on developing power and thermal models that can be used by system designs for early exploration. Specifically we develop: (1) power models for processors and accelerator blocks that accurately match gate level tools’ output and account for variability (2) thermal models that accurately account for packaging and thermal effects on leakage power, (3) floorplanning tools that minimize leakage power, and (4) sensor configuration and placement on a chip.


In this collaborative work with KAUST, we study the high level modeling and mitigation of variability and access issues in large-scale memristor-based memories. Specifically, we introduce for the first time, a closed form solution for the memristor-based memory sneak paths with out using any gating elements.

Reconfigurable computing

In this project we investigate various issues related to FPGA systems: (1) optimizing runtime reconfiguration for structures exhibiting similarities, such as filters, (2) investigating means of aggressive power reduction and mitigation schemes for the resulting lack of reliability.


For more information, please visit Professor Kurdahi’s Web Site.