Office: 3221 Engineering Hall
Lab: 2008 Anteater Instruction & Research Building
Phone: (949) 824-4155 Office
Professor Gajski’s Research
Daniel Gajski is particularly interested in requirements and specifications of embedded systems and the design process that leads from an executable specification to the final manufacturable blueprint. In order to study the design process, his group is developing new specification languages and modeling guidelines, as well as simulation, synthesis, and verification tools. In order to obtain efficient specifications and design models, they are taxonomizing models of computations, platform architectures and design styles. In order to develop efficient CAD tools, they are studying synthesis algorithms for systems, architectures, processors, controllers, datapaths, and other intellectual properties (IPs). Their further goal is to build proof-of-concept tools and prove our methodology for different application domains and tools on extensive industrial-strength examples.
Embedded Systems Methodology Group
Our main focus is currently on developing new algorithms, tools, and design flows in the context of a comprehensive SoC system-level design methodology. The results of these research efforts will flow into building different tool sets that are part of the envisioned SoC design flow.
Reference: D. Gajski, “System-Level Design Methodology,” ASP-DAC 2004 Pacifico Yokohama, Yokohama, Japan, January 27, 2004.
System-on-Chip Design Environment (SCE)Key researchers: Lukai Cai, Haobo Yu, Dongwan Shin, Andreas Gerstlauer, and Jerry Peng.
SCE is an Interactive environment for system-level design that starts from an executable specification and ends with a cycle-accurate model of the system that composes of a variety of processors, IPs, memories and buses executing the specification in a distributed fashion. SCE allows designers to make all decisions such as selecting and connecting components, partitioning computations and communications, scheduling, etc. While SCE performs automatic transaction level model generation, simulation, verification, and exploration.Reference: S. Abdi, J. Peng, H. Yu, D. Shin, A. Gerstlauer, R. Doemer, and D. Gajski, “System-on-Chip Environment: SCE Version 2.2.0 Beta Tutorial,” TR 03-41, December 2003.
Verification Through Model Algebra
Key researchers: Samar Abdi
This project defines levels of abstractions in modeling systems and rules for transformation between them in the form of a model algebra. Such well-defined models and sequence of transformation between them allow verification of model equivalence which is not possible for too independently generated models of the same design.Reference: S. Abdi and D. Gajski, “System Debugging and Verification: A New Challenge,” TR 03-31, October 1, 2003
download pdf D. Gajski and S. Abdi, “System Debugging and Verification: A New Challenge,” Verify 2003, Tokyo, Japan, November 20, 2003.
Key researchers: Mehrdad Reshadi
NISC Demo: https://www.cecs.uci.edu/~nisc/
NISC projects unites HW and SW views of computation by defining the model that unties traditional concepts of custom HW (RTL and NISC processors) with concepts of standard processors (RISC and CISC processors).Reference: D. Gajski, “NISC: The Ultimate Reconfigurable Component,” TR 03-28, October 1, 2003.
download pdfM. Reshadi and D. Gajski, “NISC Modeling and Simulation,” TR 04-08, March 2004.
download pdfD. Gajski and M. Reshadi, “NISC Application and Advantages,” TR 04-12, May 2004.
download pdfM. Reshadi and D. Gajski, “NISC Modeling and Compilation,” TR 04-33, December, 2004.
download pdfD. Gajski, and J. Trajkovic, “Communication Design for No Instruction Set Computer,” TR 05-09, July 2005.
download pdfM. Reshadi, B. Gorjiara, and D. Gajski, “NISC Technology and Preliminary Results,” TR 05-11, August 2005.
download pdfM. Reshadi, D. Gajski, “A Cycle-Accurate Compilation Algorithm for Custom Pipelined Datapaths “, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2005.
download pdfB. Gorjiara, D. Gajski, “Design Space Exploration of C Programs Using NISC: A Case-Study on DCT algorithm”, IEEE workshop on Embedded Systems for Real-Time Multimedia, 2005.
download pdfM. Reshadi, B. Gorjiara, D. Gajski, “Utilizing Horizontal and Vertical Parallelism with No-Instruction-Set Compiler for Custom Datapaths “, International Conference on Computer Design (ICCD), October 2005.
download pdfB. Gorjiara, M. Reshadi, D. Gajski, “Designing a Custom Architecture for DCT Using NISC Design Flow”, ASP-DAC’06 Design Contest, 2006.