Technical Reports
TR 24-03
Anson Fong, Yutong Wang, Rainer Doemer, “A Synthetic Graph Toolbox for Benchmarking the Grid of Processing Cells“, CECS TR 24-03, posted on June 6, 2024
TR 24-02
Yanda Li, Yutong Wang, Rainer Doemer, “Generating Synthetic Data Flow Models in SystemC TLM based on TGFF“, CECS TR 24-02, posted on May 14, 2024
TR 24-01
Xiangdong Che, Rainer Doemer, “Improved Canny Edge Detector for Parallel Color Video Processing“, CECS TR 24-01, posted on April 30, 2024
TR 23-03
Yasamin Moghaddas, Mohamad Fakih, Tyler Zhang, Mohanad Odema, Mohammad Abdullah Al Faruque, “An Integrated Corridor Management for Connected Vehicles and Park and Ride Structures using Deep Reinforcement Learning“, CECS TR 23-03, posted on August 23, 2023
TR 23-02
Zhuoqi Li, Rainer Dömer, “A Linux-based YUV Video Player”, CECS TR 23-02, posted on May 23, 2023
TR 23-01
Claudio Raccomandato, Rainer Dömer, “Modeling and Mapping of a GoogLeNet CNN on a Grid of Processing Cells”, CECS TR 23-01, posted on May 4, 2023
TR 22-04
Arya Daroui, Rainer Dömer, “A Loosely-Timed TLM-2.0 Model of a JPEG Encoder on a Checkerboard GPC“, CECS TR 22-04, posted on January 2, 2023
TR 22-03
Yutong Wang, Rainer Dömer, “A Scalable SystemC Model of a Checkerboard Grid of Processing Cells“, CECS TR 22-03, posted on January 2, 2023
TR 22-02
Vivek Govindasamy, Rainer Dömer, “Mapping of an APNG Encoder to the Grid of Processing Cells Architecture“, CECS TR 22-02, posted on January 2, 2023
TR 22-01
Rainer Dömer, “A Grid of Processing Cells (GPC) with Local Memories“, CECS TR 22-01, posted on April 18, 2022
TR 21-03
Emad Malekzadeh Arasteh, Rainer Dömer, “Systematic Evaluation of Six Models of GoogLeNet using PDES“, CECS TR 21-03, posted on September 27, 2021
TR 21-02
Yasamin Moghaddas, Tommy Nguyen, Shih-Yuan Yu, Rozhin Yasaei, Mohammad Abdullah Al Faruque, “Technical Report for HW2VEC – A Graph Learning Tool for Automating Hardware Security“, CECS TR 21-02, posted on July 30, 2021
A Tool to Flatten Multi-File SystemC Models for the RISC compiler
Yutong Wang, Rainer Domer, “A Tool to Flatten Multi-File SystemC Models for the RISC compiler“, CECS TR 21-01, posted on March 1, 2021
A SystemC Model of a PNG Encoder
Vivek Govindasamy, Rainer Domer, “A SystemC Model of a PNG Encoder“, CECS TR 20-02, posted on January 4, 2021
Deep Code Curator – code2graph Part-II
Shih-Yuan Yu, Arnav Vaibhav Malawade, Aung Myat Thu, Mohammad Abdullah Al Faruque, “Deep Code Curator – code2graph Part-II”, CECS TR 20-01, posted on May 20, 2020
Deep Code Curator – code2graph Part-I
Shih-Yuan Yu, Ahmet Salih Aksakal, Sujit Rokka Chhetri, Mohammad Abdullah Al Faruque, “Deep Code Curator – code2graph Part-I” (Primarily title: “Deep Code Curator – Technical Report on Code2Graph”), CECS TR 19-01, posted on May 15, 2020
RISC Compiler and Simulator, Release V0.6.0: Out-of-Order Parallel Simulatable SystemC Subset
Guantao Liu, Tim Schmidt, Zhongqi Cheng, Daniel Mendoza and Rainer Domer, “RISC Compiler and Simulator, Release V0.6.0: Out-of-Order Parallel Simulatable SystemC Subset“, CECS TR 19-04, posted on October 9, 2019
Simulation Infrastructure and System Modeling for Control-theory based Quality Configurable Memories
Biswadip Maity, Majid Shoushtari, Amir M. Rahmani and Nikil Dutt, “Simulation Infrastructure and System Modeling for Control-theory based Quality Configurable Memories“, CECS TR 19-03, posted on July 08, 2019
Deep Code Curator – Technical Report on Code2Graph
Shih-Yuan Yu, Ahmet Salih Aksakal, Sujit Rokka Chhetri, Mohammad Abdullah Al Faruque, “Deep Code Curator – Technical Report on Code2Graph”, CECS TR 19-01, posted on May 22, 2019
RISC Compiler and Simulator, Release V0.5.0: Out-of-Order Parallel Simulatable SystemC Subset
Guantao Liu, Tim Schmidt, Zhongqi Cheng, Daniel Mendoza and Rainer Domer, “RISC Compiler and Simulator, Release V0.5.0: Out-of-Order Parallel Simulatable SystemC Subset”, CECS TR 18-03, posted on October 3, 2018
System Level CPS design using Non-Euclidean Training method
Jiang Wan, Arquimedes Canedo, Mohammad Abdullah Al Faruque, “System Level CPS design using Non-Euclidean Training method“, CECS TR 18-02, posted on June 6, 2018
Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines
Sajjad Taheri, Jin Heo, Payman Behnam, Alexander Veidenbaum and Alexandru Nicolau, “Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines”, CECS TR 18-01, posted on March 8, 2018
Digital Twin of Manufacturing Systems
Sujit Rokka Chhetri, Sina Faezi, Mohammad Abdullah Al Faruque, “Digital Twin of Manufacturing Systems”, CECS TR 17-07, posted on December 5, 2017
A Tool for Visualization of SystemC Modules
Daniel Mendoza, Rainer Dömer, “A Tool for Visualization of SystemC Modules”, CECS TR 17-06, posted on November 8, 2017
RISC Compiler and Simulator: Release Vo.4.0: Out-of-Order Parallel Simulatable SystemC Subset
Guantao Liu, Tim Schmidt, Zhongqi Cheng, Rainer Dömer, “RISC Compiler and Simulator, Release V0.4.0: Out-of-Order Parallel Simulatable SystemC Subset”, CECS TR 17-05, posted on July 31, 2017
Software and Hardware Implementation of Lattice-Cased Cryptography Schemes
Hamid Nejatollahi, Nikil Dutt, Sandip Ray, Francesco Regazzoni, Indranil Banerjee, Rosario Cammarota, “Software and Hardware Implementation of Lattice-based Cryptography Schemes”, CECS TR 17-04, posted on November 9, 2017 (revised 5/31/18)
A Survey of Techniques for Approximate Memory Management
Majid Shoushtari, Nikil Dutt, “A Survey of Techniques for Approximate Memory Management”, CECS TR 17-03, posted on January 16, 2018
OpenCV.js: Computer Vision Processing for the Web
Sajjad Taheri, Alexander Veidenbaum, Alexandru Nicolau, Mohammad R. Haghighat, “OpenCV.js: Computer Vision Processing for the Web“, CECS TR 17-02, posted on July 24, 2017
Using Hardware Counters to Predict Vectorization
Neftali Watkinson, Aniket Shivam, Zhi Chen, Alex Veidenbaum, Alexandru Nicola, “Using Hardware Counters to Predict Vectorization” CECS TR 17-01, posted on May 19, 2017
A SystemC Model for N-body problems and its Parallel Design Space Exploration
Kasra Moazzemi, Rainer Doemer, Aparna Chandramowlishwaran, “A SystemC model for N-body problems and its Parallel Design Space Exploration” CECS TR 16-09, posted on November 29, 2016
SPM-vSharE: Memory Management in SPM-based Many-core Embedded Systems
Majid Shoushtari, Bryan Donyanavard, Luis Angel D. Bathen, Nikil Dutt, “SPM-vSharE: Memory Management in SPM-based Many-core Embedded Systems” CECS TR 16-08, posted on November 28, 2016
A Light Weight SystemC Library for Faster Compilation
Farah Arabi, Tim Schmidt, Rainer Dőmer, “A Light Weight SystemC Library for Faster Compilation” CECS TR 16-07, posted on October 24, 2016
RISC Compiler and Simulator, Beta Release V0.3.0:Out-of-Order Parallel Simulatable SystemC Subset
Design Space Exploration Framework for Memory Exploration in Heterogeneous Architectures
Kasra Moazzemi, Chen-Ying Hsieh, Nikil Dutt, “Design Space Exploration Framework for Memory Exploration in Heterogeneous Architectures” CECS TR 16-03, posted on July 7, 2016
Using HSFMs to Model Mobile Gaming Behavior for Energy Efficient DVFS Governors
Jurn-Gyu Park, Hoyeonjiki Kim, Nikil Dutt, Sung-Soo Lim, “Using HSFMs to Model Mobile Gaming Behavior for Energy Efficient DVFS Governors” CECS TR 16-02, posted on June 22, 2016
Forensics of Thermal Side-Channel in Additive Manufacturing Systems
Mohammad Abdullah Al Faruque, Sujit Rokka Chhetri, Sina Faezi, Arquimedes Canedo, “Forensics of Thermal Side-Channel in Additive Manufacturing Systems” CECS TR 16-01, posted on January 20, 2016
Cooperative CPU-GPU Frequency Capping (Co-Cap) for Energy Efficient Mobile Gaming
Jurn-Gyu Park, Chen0Ying Hsieh, Nikil Dutt, Sung-Soo Lim, “Cooperative CPU-GPU Frequency Capping (Co-Cap) for Energy Efficient Mobile Gaming,” CECS TR 15-05, posted on December 11, 2015
SIMD-Based Soft Error Detection
Zhi Chen, Alex Nicolau, Alexander V. Veidenbaum, “SIMD-Based Soft Error Detection,” CECS TR 15-04, posted on November 23, 2015
Fast Fast-J GPU Codes
Fausto Artico, Michael J. Prather, Alexander V. Veidenbaum, Alexandru Nicolau, “Fast Fast-J GPU Codes,” CECS TR 15-03, posted on November 18, 2015
RISC Compiler and Simulator, Alpha Release V0.2.1: Out-of-Order Parallel Simulatable SystemC Subset
Guantao Liu, Tim Schmidt, Rainer Dömer, “RISC Compiler and Simulator, Alpha Release V0.2.1: Out-of-Order Parallel Simulatable SystemC Subset,” CECS TR 15-02, posted on October 30, 2015