Technical Reports
HDLGen: Architecture Description Language driven HDL Generation for Pipelined Processors
N. Dutt, A. Kejariwal, P. Mishra, J. Astrom, "HDLGen: Architecture Description Language driven HDL Generation for Pipelined Processors," TR 03-04, February 3, 2003. download pdf
POSIX-Compliant Portable Code Synthesis for Embedded Systems
A. Nacul, S. Choudhuri, and T. Givargis, “POSIX-Compliant Portable Code Synthesis for Embedded Systems,” TR 03-36, November 25, 2003. download pdf
Integrated Power Management for Video Streaming to Mobile Handheld Devices
R. Cornea, S. Mohapatra, N. Dutt, A. Nicolau, N. Venkatasubramanian, "Integrated Power Management for Video Streaming to Mobile Handheld Devices," TR 03-19, May 2003. download pdf
Channel Mapping in System Level Design
D. D. Gajski and L. Cai, "Channel Mapping in System Level Design," TR 03-03, January 7, 2003. download pdf
Leakage Aware Dynamic Voltage Scaling for Real Time Embedded Systems
R. Jejurikar, C. Pereira, and R. Gupta, "Leakage Aware Dynamic Voltage Scaling for Real Time Embedded Systems," TR 03-35, November 30, 2003. download pdf
Automatic Software Generation for System Level Design
H. Yu, R. Doemer, and D. Gajski, "Automatic Software Generation for System Level Design," TR 03-18, May 14, 2003. download pdf
System Design Methodology and Tools
D. D. Gajski, J. Peng, A. Gerstlauer, H. Yu, and D. Shin, "System Design Methodology and Tools," TR 03-02, January 12, 2003. download pdf
Dynamic Voltage and Cache Reconfiguration for Low Power
A. Nacul and T. Givargis, “Dynamic Voltage and Cache Reconfiguration for Low Power,” TR 03-34, November 7, 2003. download pdf
A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor
S. Pasricha, P. Biswas, P. Mishra, A. Shrivastava, A. Mandal, N. Dutt, and A. Nicolau, "A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor," TR 03-17, April 2003. download pdf
Adaptive Online Cache Reconfiguration for Low Power Systems
T. Givargis and A. Nacul, "Adaptive Online Cache Reconfiguration for Low Power Systems," TR 03-01, April 23, 2003. download pdf
Automatic Generation of Bus Functional Models from Transaction Level Models
D. Shin, S. Abdi, and D. Gajski, “Automatic Generation of Bus Functional Models from Transaction Level Models,” TR 03-33, November 18, 2003. download pdf
Greedy and Heuristic-based Algorithms for Synthesis of Complex Instructions in Heterogeneous-Connectivity-based DSPs
P. Biswas and N. Dutt, "Greedy and Heuristic-based Algorithms for Synthesis of Complex Instructions in Heterogeneous-Connectivity-based DSPs," TR 03-16, April 2003. download pdf
Leakage Power Estimation in SRAMs
M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir, "Leakage Power Estimation in SRAMs," TR 03-32, October 24, 2003. download pdf
Energy Efficient Communication for Reliability and Quality Aware Sensor Networks
C. Pereira, S. Gupta, K. Niyogi, I. Lazaridis, S. Mehrotra, and R. Gupta, “Energy Efficient Communication for Reliability and Quality Aware Sensor Networks,” TR 03-15, April 21, 2003. download pdf
System Debugging and Verification: A New Challenge
S. Abdi and D. Gajski, "System Debugging and Verification: A New Challenge," TR 03-31, October 1, 2003 download pdf
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, "Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow," TR 03-14, April 2003. download pdf
Communication Abstractions for System-Level Design and Synthesis
A. Gerstlauer, "Communication Abstractions for System-Level Design and Synthesis," TR 03-30, October 24, 2003. download pdf
C to SpecC Conversion Style
D. D. Gajski and K. Ramineni, "C to SpecC Conversion Style," TR 03-13, April 4, 2003. download pdf
Provably Correct Architecture Refinement
S. Abdi and D. Gajski, "Provably Correct Architecture Refinement," TR 03-29, September 30, 2003. download pdf
RTOS Scheduling in Transaction Level Models
D. D. Gajski, H. Yu, and A. Gerstlauer, "RTOS Scheduling in Transaction Level Models," TR 03-12, March 20, 2003. download pdf
NISC: The Ultimate Reconfigurable Component
D. Gajski, "NISC: The Ultimate Reconfigurable Component," TR 03-28, October 1, 2003. download pdf
Comparison of SpecC and SystemC Languages for System Design
D. D. Gajski, L. Cai, and S. Verma, "Comparison of SpecC and SystemC Languages for System Design," TR 03-11, May 15, 2003. download pdf
An Algorithm to Avoid Power Command Jitter in Middleware-Based Distributed Embedded Systems
B. Gorjiara, P. Chou, N. Bagherzadeh, "An Algorithm to Avoid Power Command Jitter in Middleware-Based Distributed Embedded Systems," TR 03-47, July 2003. download pdf
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures
N. Bansal, S. Gupta, N. Dutt, A. N, and R. Gupta, "Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures," TR03-27, August 2003. download pdf
Transaction Level Modeling in System Level Design
D. D. Gajski and L. Cai, "Transaction Level Modeling in System Level Design," TR 03-10, March 28, 2003. download pdf
GX-GUI: A General Extensible Technique for 2-D Interaction with VR Applications
B. Gorjiara, F. Kuester, P. Chou, and M. Reshadi, "GX-GUI: A General Extensible Technique for 2-D Interaction with VR Applications," TR 03-46, January 2003. download pdf
System-On-Chip Component Models
A. Gerstlauer, L.Cai, D. Shin, R. Doemer, and D. Gajski, "System-On-Chip Component Models," TR 03-26, August 11, 2003. Complete TR is available upon request
G.729E Algorithm Optimization for ARM926EJ-S Processor
D. D. Gajski, A. Tripathi, and S. Verma, "G.729E Algorithm Optimization for ARM926EJ-S Processor," TR 03-09, March 21, 2003. download pdf
System-on-Chip Environment (SCE Version 2.2.0 Beta): Manual
L. Cai, A. Gerstlauer, S. Abdi, J. Peng, D. Shin, H. Yu, R. Doemer, D. Gajski, "System-on-Chip Environment (SCE Version 2.2.0 Beta): Manual," TR 03-45, December 2003. download pdf
D. Shin, A. Gerstlauer, R. Doemer, and D. Gajski, "C-based Interactive RTL Design Methodology," TR 03-42, December 1, 2003. download pdf
Architecture Description Language driven Validation of Dynamic Behavior in Pipelined Processor Specifications
P. Mishra, N. Dutt and H. Tomiyama, "Architecture Description Language driven Validation of Dynamic Behavior in Pipelined Processor Specifications," TR 03-25, July 28, 2003. download pdf
Automatic Communication Refinement for System Level Design
D. D. Gajski and S. Abdi, "Automatic Communication Refinement for System Level Design," TR 03-08, March 7, 2003. download pdf
Mapping Loops on Coarse-Grain Reconfigurable Architectures Using Memory Operation Sharing
J. Leei, K. Choi, N. Dutt, “Mapping Loops on Coarse-Grain Reconfigurable Architectures Using Memory Operation Sharing," TR 02-34, September 2002. download pdf
Interface Synthesis from Protocol Specification
D. Shin, D. D. Gajski, “Interface Synthesis from Protocol Specification,” TR 02-13, April 12, 2002. download pdf
System-Level Design Flow: What is needed and what is not
D. D. Gajski, “System-Level Design Flow: What is needed and what is not," TR 02-33, November 26, 2002. download pdf
Queue Generation Algorithm for Interface Synthesis
D. Shin, D. D. Gajski, “Queue Generation Algorithm for Interface Synthesis,” TR 02-12, April 11, 2002. download pdf
Variable Mapping of System Level Design
D. D. Gajski, L. Cai, “Variable Mapping of System Level Design," TR 02-32, October 8, 2002. download pdf
Scheduling in RTL Design Methodology
D. Shin, D. D. Gajski, “Scheduling in RTL Design Methodology,” TR 02-11, April 12, 2002. download pdf
Grouping-Based Architecture Exploration of System-Level Design
D. D. Gajski, L. Cai, “Grouping-Based Architecture Exploration of System-Level Design," TR 02-31, August 16, 2002. download pdf
Optimal Indexing for Cache Miss Reduction in Embedded Systems
T. Givargis, “Optimal Indexing for Cache Miss Reduction in Embedded Systems,” TR 02-10, July 4, 2002. download pdf
Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis
S. Gupta, N. Savoiu, N. Dutt, R. Gupta, A. Nicolau, “Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis," TR 02-29, October 1, 2002. download pdf