Technical Reports
System-On-Chip Component Models
A. Gerstlauer, L.Cai, D. Shin, R. Doemer, and D. Gajski, "System-On-Chip Component Models," TR 03-26, August 11, 2003. Complete TR is available upon request
G.729E Algorithm Optimization for ARM926EJ-S Processor
D. D. Gajski, A. Tripathi, and S. Verma, "G.729E Algorithm Optimization for ARM926EJ-S Processor," TR 03-09, March 21, 2003. download pdf
System-on-Chip Environment (SCE Version 2.2.0 Beta): Manual
L. Cai, A. Gerstlauer, S. Abdi, J. Peng, D. Shin, H. Yu, R. Doemer, D. Gajski, "System-on-Chip Environment (SCE Version 2.2.0 Beta): Manual," TR 03-45, December 2003. download pdf
D. Shin, A. Gerstlauer, R. Doemer, and D. Gajski, "C-based Interactive RTL Design Methodology," TR 03-42, December 1, 2003. download pdf
Architecture Description Language driven Validation of Dynamic Behavior in Pipelined Processor Specifications
P. Mishra, N. Dutt and H. Tomiyama, "Architecture Description Language driven Validation of Dynamic Behavior in Pipelined Processor Specifications," TR 03-25, July 28, 2003. download pdf
Automatic Communication Refinement for System Level Design
D. D. Gajski and S. Abdi, "Automatic Communication Refinement for System Level Design," TR 03-08, March 7, 2003. download pdf
System-on-Chip Environment: SCE Version 2.2.0 Beta Tutorial
S. Abdi, J. Peng, H. Yu, D. Shin, A. Gerstlauer, R. Doemer, and D. Gajski, "System-on-Chip Environment: SCE Version 2.2.0 Beta Tutorial," TR 03-41, December 2003. download pdf
Novel Techniques to Improve Branch Prediction Accuracy for Embedded Processors in the Presence of Context Switches
S. Pasricha and A. Veidenbaum, "Novel Techniques to Improve Branch Prediction Accuracy for Embedded Processors in the Presence of Context Switches," TR 03-24, August 2003. download pdf
Dual-Mode Frequency Inheritance Algorithm for Energy Aware Task Scheduling with Task Synchronization
R. Gupta, R. Jejurikar, and C. Periera, "Dual-Mode Frequency Inheritance Algorithm for Energy Aware Task Scheduling with Task Synchronization," TR 03-07, February 28, 2003. download pdf
FIFO Power Optimization for On-Chip Networks
S. Banerjee and N. Dutt, "FIFO Power Optimization for On-Chip Networks," TR 03-40, December 19, 2003. download pdf
On Demand Paging Using Bluetooth Radios on 802.11 Based Networks
Y. Agarwal and R. Gupta, "On Demand Paging Using Bluetooth Radios on 802.11 Based Networks," TR 03-22, June 2003. download pdf
Formal Verification of Specification Partitioning
D. D. Gajski, S. Abdi, "Formal Verification of Specification Partitioning," TR 03-06, April 23, 2003. download pdf
Petri Net-based Thread Composition for Improved System Level Simulation
N. Savoiu, S. Shukla, and R. Gupta, "Petri Net-based Thread Composition for Improved System Level Simulation," TR 03-39, December 29, 2003. download pdf
System-On-Chip Specification Style Guide
A. Gerstlauer, K. Ramineni, R. Doemer, and D. Gajski, "System-On-Chip Specification Style Guide," TR 03-21, June 25, 2003. download pdf
ReXsim: A Retargetable Framework for Instruction-Set Architecture Simulation
N. Dutt, M. Reshadi, P. Mishra, N. Bansal, "ReXsim: A Retargetable Framework for Instruction-Set Architecture Simulation," TR 03-05, February 10, 2003. download pdf
Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices
A. Kejariwal, S. Gupta, A. Nicolau, N. Dutt, and R. Gupta, "Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices," TR 03-38, November 2003. download pdf
Interface Synthesis using Memory Mapping for an FPGA Platform
M. Luthra, S. Gupta, N. Dutt. R. Gupta, A. Nicolau, "Interface Synthesis using Memory Mapping for an FPGA Platform," TR 03-20, June 25, 2003. download pdf
HDLGen: Architecture Description Language driven HDL Generation for Pipelined Processors
N. Dutt, A. Kejariwal, P. Mishra, J. Astrom, "HDLGen: Architecture Description Language driven HDL Generation for Pipelined Processors," TR 03-04, February 3, 2003. download pdf
POSIX-Compliant Portable Code Synthesis for Embedded Systems
A. Nacul, S. Choudhuri, and T. Givargis, “POSIX-Compliant Portable Code Synthesis for Embedded Systems,” TR 03-36, November 25, 2003. download pdf
Integrated Power Management for Video Streaming to Mobile Handheld Devices
R. Cornea, S. Mohapatra, N. Dutt, A. Nicolau, N. Venkatasubramanian, "Integrated Power Management for Video Streaming to Mobile Handheld Devices," TR 03-19, May 2003. download pdf
Channel Mapping in System Level Design
D. D. Gajski and L. Cai, "Channel Mapping in System Level Design," TR 03-03, January 7, 2003. download pdf
Leakage Aware Dynamic Voltage Scaling for Real Time Embedded Systems
R. Jejurikar, C. Pereira, and R. Gupta, "Leakage Aware Dynamic Voltage Scaling for Real Time Embedded Systems," TR 03-35, November 30, 2003. download pdf
Automatic Software Generation for System Level Design
H. Yu, R. Doemer, and D. Gajski, "Automatic Software Generation for System Level Design," TR 03-18, May 14, 2003. download pdf
System Design Methodology and Tools
D. D. Gajski, J. Peng, A. Gerstlauer, H. Yu, and D. Shin, "System Design Methodology and Tools," TR 03-02, January 12, 2003. download pdf
Dynamic Voltage and Cache Reconfiguration for Low Power
A. Nacul and T. Givargis, “Dynamic Voltage and Cache Reconfiguration for Low Power,” TR 03-34, November 7, 2003. download pdf
A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor
S. Pasricha, P. Biswas, P. Mishra, A. Shrivastava, A. Mandal, N. Dutt, and A. Nicolau, "A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor," TR 03-17, April 2003. download pdf
Adaptive Online Cache Reconfiguration for Low Power Systems
T. Givargis and A. Nacul, "Adaptive Online Cache Reconfiguration for Low Power Systems," TR 03-01, April 23, 2003. download pdf
Automatic Generation of Bus Functional Models from Transaction Level Models
D. Shin, S. Abdi, and D. Gajski, “Automatic Generation of Bus Functional Models from Transaction Level Models,” TR 03-33, November 18, 2003. download pdf
Greedy and Heuristic-based Algorithms for Synthesis of Complex Instructions in Heterogeneous-Connectivity-based DSPs
P. Biswas and N. Dutt, "Greedy and Heuristic-based Algorithms for Synthesis of Complex Instructions in Heterogeneous-Connectivity-based DSPs," TR 03-16, April 2003. download pdf
Leakage Power Estimation in SRAMs
M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir, "Leakage Power Estimation in SRAMs," TR 03-32, October 24, 2003. download pdf
Energy Efficient Communication for Reliability and Quality Aware Sensor Networks
C. Pereira, S. Gupta, K. Niyogi, I. Lazaridis, S. Mehrotra, and R. Gupta, “Energy Efficient Communication for Reliability and Quality Aware Sensor Networks,” TR 03-15, April 21, 2003. download pdf
Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV
P. Mishra, N. Dutt, “Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV,” TR 02-26, September 13, 2002. download pdf
Specification Tuning of System-Level Design
L. Cai and D Gajski, "Specification Tuning of System-Level Design,” TR 02-20, June 6, 2002. download pdf
The Formal Execution Semantics of SpecC
W. Mueller, R. Doemer, A. Gerstlauer, “The Formal Execution Semantics of SpecC,” TR 02-04, January 11, 2002. download pdf
Analytical Design Space Exploration of Caches for Embedded Systems
A. Ghosh, T. Givargis, “Analytical Design Space Exploration of Caches for Embedded Systems,” TR 02-27, September 11, 2002. download pdf
A Framework for Memory Subsystem Exploration
P. Mishra, M. Mamidipaka, N. Dutt, “A Framework for Memory Subsystem Exploration,” TR 02-19, May 24, 2002. download pdf
Efficiency and Optimality of Static Slowdown for Periodic Tasks in Real-Time Embedded Systems
R. Jejurikar, R. Gupta, “Efficiency and Optimality of Static Slowdown for Periodic Tasks in Real-Time Embedded Systems,” TR 02-03, March 19, 2002. download pdf
Parallelization Optimization of System-Level Specification
L. Cai, D. D. Gajski, “Parallelization Optimization of System-Level Specification,” TR 02-18, June 1, 2002. download pdf
A Software Architecture for Building Power Aware Real Time Operating Systems
C. Pereira, V. Raghunathan, S. Gupta, R. Gupta, M. Srivastava, “A Software Architecture for Building Power Aware Real Time Operating Systems,” TR 02-02, March 14, 2002. download pdf
System-Level Abstraction Semantics
A. Gerstlauer, D. D. Gajski, “System-Level Abstraction Semantics,” TR 02-17, July 12, 2002. download pdf
Aspect + Gamma = AspectGamma: A Framework for Aspect Orineted Programming
M. Mousavai, G. Russello, M. Chaudron, M. Reniers, T. Basten, A. Corsaro, S. Shukla, R. Gupta, D. Schmidt, “Aspect + Gamma = AspectGamma: A Framework for Aspect Orineted Programming,” TR 02-01, March 1, 2002. download pdf