TABLE OF CONTENTS ED&TC 97

Sessions: [1A] [1B] [1C] [2A] [2B] [2C] [2D] [3A] [3B] [3C] [3D] [4A] [4B] [4C] [4D] [5A] [5B] [5C] [5D] [6A] [6B] [6C] [7A] [7B] [7C] [8A] [8B] [8C] [9A] [9B] [9C] [10A] [10B] [10C] [11A] [11B] [11C] [11D] [Poster]

Organizing and Program Committee
Technical Program Committee
Keynote Speakers
Welcome Message
Tutorials
Best Paper Award
List of Reviewers

Session 1A: System Analysis Techniques and Applications

Moderators: P. Marwedel, University of Dortmund, Germany, F. Kurdahi, University of California, Irvine, USA
RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems [pp 2]
A. Dasdan, A. Mathur, and R.K. Gupta

Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications [pp 7]
P.R. Panda, N.D. Dutt, and A. Nicolau

Interface Timing Verification with Delay Correlation Using Constraint Logic Programming [pp 12]
P. Girodias and E. Cerny

Session 1B: Sequential ATPG

Moderators: R. Ubar, Tallinn University, Estonia, B. Straube, Fraunhofer IIS/EAS Dresden, Germany
Sequential Circuit Test Generation Using Dynamic State Traversal [pp 22]
M.S. Hsiao, E.M. Rudnick, and J.H. Patel

MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits [pp 29]
A. Dargelas, C. Gauthron, and Y. Bertrand

New Static Compaction Techniques of Test Sequences for Sequential Circuits [pp 37]
F. Corno, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda

Session 1C: Design and Design Methodology for Analog Circuits

Moderators: J. Pikkarainen, Nokia Mobile Phones, Finland, F. Maloberti, University of Pavia, Italy
A Methodology for Designing Continuous-Time Sigma-Delta Modulators [pp 46]
P. Benabes, M. Keramat, and R. Kielbasa

A CMOS Low-Voltage, High-Gain Op-Amp [pp 51]
G.N. Lu and G. Sou

High-Level Synthesis of Analog Sensor Interface Front-Ends [pp 56]
S. Donnay, G. Gielen, W. Sansen, W. Kruiskamp, D. Leenaerts, and W. van Bokhoven

Panel P1 - How to Introduce Advanced Design Technology in Qualified Industrial Design Flows?
Coordinator: I. Bolsens, IMEC, Belgium
Moderator: P. De Wilde, TU Delft/DIMES, The Netherlands

Panel:
P. Reynaert, Mentor Graphics, Belgium
P. Pype, Coware, USA
R. Jain, University of California, Los Angeles, USA
P. Odent, Philips, The Netherlands
P. Paulin, ST, France
K-P. Estola, Nokia Mobile Phones, Finland
H. Cloetens, Philips, The Netherlands

Session 2B: Advances in Built-In Self-Test

Moderators: Y. Zorian, LogicVision, USA, E. Aas, University of Trondheim, Norway
Structural BIST Insertion Using Behavioral Test Analysis [pp 64]
M. Nourani and C. Papachristou

On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs [pp 69]
C. Dufaza and Y. Zorian

Cellular Automata for Generating Deterministic Test Sequences [pp 77]
D. Kagaris and S. Tragoudas

Session 2C: Synthesis of Controllers

Moderators: J. Jess, Eindhoven, University of Technology, The Netherlands, B. Lin, IMEC, Belgium
Fast Controllers for Data Dominated Applications [pp 84]
A. Hertwig and H-J. Wunderlich

Random Benchmark Circuits with Controlled Attributes [pp 90]
K. Iwama, K. Hino, H. Kurokawa, and S. Sawada

Technology Mapping of Speed-Independent Circuits Based on Combinational Decomposition and Resynthesis [pp 98]
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev

Session 2D: Microsystems Design I

Moderators: J.-M. Karam, TIMA, Grenoble, France, L. Claesen, IMEC, Belgium
Generation of the HDL-A-Model of a Micromembrane from Its Finite- Element-Description [pp 108]
K. Hofmann, M. Glesner, N. Sebe, A. Manolescu, S. Marco, J. Samitier, J-M. Karam, and B. Coutois

Microsystem Design Using Simulator Coupling [pp 113]
W. Wünsche, C. Clauß, P. Schwarz, and F. Winkler

Modeling and Simulation of Electromechanical Transducers in Microsystems Using an Analogue Hardware Description Language [pp 119]
B. Romanowicz, M. Laudon, P. Lerch, P. Renaud, H.P. Amann, A. Boegli, V. Moser, and F. Pellandini

Session 3A: Software Generation for Embedded Processors

Moderators: R. Ernst, Technical University of Braunschweig, Germany, W. Wolf, Princeton University, USA
Delay Management for Programmable Video Signal Processors [pp 126]
M.L.G. Smeets, E.H.L. Aarts, G. Essink, and E.A. de Kock

Hierarchical Scheduling and Allocation of Multirate Systems on Heterogeneous Multiprocessors [pp 134]
Y. Li and W. Wolf

Retargetable Generation of Code Selectors from HDL Processor Models [pp 140]
R. Leupers and P. Marwedel

Session 3B: Register Transfer Level Test Synthesis

Moderators: H.-J. Wunderlich, University of Stuttgart, Germany, A.J. van de Goor, Technical University of Delft, The Netherlands
An RTL Methodology to Enable Low Overhead Combinational Testing [pp 146]
S. Bhattacharya, S. Dey, and B. Sengupta

A Controller Testability Analysis and Enhancement Technique [pp 153]
X. Gu, E. Larsson, K. Kuchinski, and Z. Peng

Analyzing Testability from Behavioral to RT Level [pp 158]
M.L. Flottes, R. Pires, and B. Rouzeyre

Session 3C: BDDs and Formal Verification

Moderators: N. Fristacky, Slovak Technical University, Slovakia, R. Kumar, FZI, Karlsruhe, Germany
Fast and Efficient Construction of BDDs by Reordering Based Synthesis [pp 168]
A. Hett, R. Drechsler, and B. Becker

Verification and Synthesis of Counters Based on Symbolic Techniques [pp 176]
G. Cabodi, P. Camurati, L. Lavagno, and S. Quer

Using MTBDDs for Discrete Timed Symbolic Model Checking [pp 182]
T. Kropf and J. Ruf

Session 3D: Microsystems Design II

Moderators: M. Rencz, Technical University of Budapest, Hungary, M. Glesner, TH Darmstadt, Germany
Analysis of 3D Conjugate Heat Transfers in Electronics [pp 190]
J.P. Fradin, L. Molla, and B. Desaunettes

Smart Sensor System Application: An Integrated Compass [pp 195]
R.J.W.T. Tangelder, G. Diemel, and H.G. Kerkhoff

Automatic Transfer of Parametric FEM Models into CAD-Layout Formats for Top-Down Design of Microsystems [pp 200]
M. Lang, D. David, and M. Glesner

Panel P3 - What Will Be the Right Test Methodology for the Year 2005?
Coordinator: I. Bolsens, IMEC, Belgium
Moderator: K. Baker, Philips, The Netherlands

Panel:
B. Schneider, Microlex, Denmark
P. De Pauw, Alcatel-Mietec, Belgium
T. Williams, IBM, Boulder, USA
B. Grubel, Texas Instruments, USA
S. Athan, Univ. Florida, USA

Session 4B: High Performance Architectures for Multimedia and Communication ASICs

Moderators: I. Bolsens, IMEC, Belgium, Y. Torroja, Universidad Politecnica de Madrid, Spain
Highly Scalable Parallel Parametrizable Architecture of the Motion Estimator [pp 208]
R. Cmar and S. Vernalde

Design and Implementation of a Coprocessor for Cryptography Applications [pp 213]
A. Royo, J. Mor´n, and J.C. López

On the Way to the 2.5 Gbits/s ATM Network ATM Multiplexer Demultiplexer ASIC [pp 218]
J. Riesco, J.C. Díaz, L.A. Merayo, J.L. Conesa, C. Santos, and E. Juárez

Session 4C: Decision Diagrams and Diagnosis

Moderators: R. Drechsler, University of Freiburg, Germany, E. Macii, Politecnico de Torino, Italy
Solving Graph Optimization Problems with ZBDDs [pp 224]
O. Coudert

Minimizing ROBDD Sizes of Incompletely Specified Boolean Functions by Exploiting Strong Symmetries [pp 229]
C. Scholl, S. Melchior, G. Hotz, and P. Molitor

Connection Error Location and Correction in Combinational Circuits [pp 235]
A.M. Wahba and D. Borrione

Session 4D: Performance Modeling

Moderators: M. Sarrafzadeh, Northwestern University, USA, M. Servit, Czech Technical University, Czech Republic
Shaping a VLSI Wire to Minimize Elmore Delay [pp 244]
J.P. Fishburn

Inductance Analysis of On-Chip Interconnects [pp 252]
S. Kundu and U. Ghoshal

Cartesian Multipole Based Numerical Integration for 3D Capacitance Extraction [pp 256]
U. Geigenmüller and N.P. van der Meijs

Session 5A: Hot Topic HT1 - Networked CAD Systems

Coordinator: E. Van Utteren, Philips, Eindhoven, The Netherlands
Moderator: G. De Micheli, Stanford University, USA

Session 5B: Progress in IDDQ Test Technology

Moderators: R. Segers, Philips ED&T, The Netherlands, H. Vierhaus, Technical University of Cottbus, Germany
CCII+ Current Conveyor Based BIC Monitor for IDDQ Testing of Complex CMOS Circuits [pp 266]
V. Stopjaková and H. Manhaeve

Deep Sub-Micron IDDQ Testing: Issues and Solutions [pp 271]
M. Sachdev

A Production-Oriented Measurement Method for Fast and Exhaustive Iddq Tests [pp 279]
B. Laquai, H. Richter, and H. Werkmann

Session 5C: Architecture Exploration

Moderators: J. van Meerbergen, Philips Research Labs, The Netherlands, R. Ernst, Technical University of Braunschweig, Germany
Library Mapping for Memories [pp 288]
P.K. Jha and N.D. Dutt

Architectural Exploration and Optimization for Counter Based Hardware Address Generation [pp 293]
M. Miranda, M. Kaspar, F. Catthoor, and H. De Man

RTL Synthesis with Physical and Controller Information [pp 299]
M. Xu and F.J. Kurdahi

Session 5D: Layout Design

Moderators: R. Otten, Delft University of Technology, The Netherlands, M. Sarrafzadeh, Northwestern University, USA
Two-Way Partitioning Based on Direction Vector [pp 306]
K.S. Seong and C.M. Kyung

Multi-Layer Chip-Level Global Routing Using an Efficient Graph-Based Steiner Tree Heuristic [pp 311]
L-C.E. Liu and C. Sechen

A Gridless Multi-Layer Router for Standard Cell Circuits Using CTM Cells [pp 319]
H-P. Tseng and C. Sechen

Session 6A: Hot Topic HT2 - Deep Submicron CAD

Coordinator: E. Van Utteren, Philips, Eindhoven, The Netherlands
Moderator: Ralph Otten, Delft University of Technology, The Netherlands

Session 6B: Testability Solutions for Regular Structures

Moderators: J. Figueras, Universidad Politecnica de Catalunya, Spain, T. Williams, IBM, Boulder, USA
A Programmable Boundary Scan Technique for Board-Level, Parallel Functional Duplex March Testing of Word-Oriented Multiport Static RAMs [pp 330]
K. Chakraborty and P. Mazumder

Fault-Secure Shifter Design: Results and Implementations [pp 335]
R.O. Duarte, M. Nicolaidis, H. Bederr, and Y. Zorian

High-Speed C-Testable Systolic Array Design for Galois-Field Inversion [pp 342]
C-T. Huang and C-W. Wu

Session 6C: Data Converter Test Issues

Moderators: A. Richardson, University of Lancaster, UK, H. Kerkhoff, University of Twente, The Netherlands
Efficient and Accurate Testing of Analog-to-Digital Converters Using Oscillation-Test Method [pp 348]
K. Arabi and B. Kaminska

Built-In Self-Test Methodology for A/D Converters [pp 353]
R. de Vries, T. Zwemstra, E.M.J.G. Bruls, and P.P.L. Regtien

Reconfigurable Data Converter as a Building Block for Mixed-Signal Test [pp 359]
E.K.F. Lee

Session 7A: Hot Topic HT3 - Multichip Packages for Consumer Applications

Coordinator: E. Van Utteren, Philips, Eindhoven, The Netherlands
Moderator: M. Muris, Philips Research Labs (ED&T), The Netherlands

Session 7B: Extensions and Acceleration of Discrete Event Simulation

Moderators: P. Schwarz, Fraunhofer EAS Dresden, Germany, M. Koch, University of Rostock, Germany
VHDL Extensions for Complex Transmission Line Simulation [pp 368]
P. Walker and S. Ghosh

Acceleration of Behavioral Simulation on Simulation Specific Machines [pp 373]
M. Shoji, F. Hirose, S. Shimogori, S. Kowatari, and H. Nagai

Exploiting Temporal Independence in Distributed Preemptive Circuit Simulation [pp 378]
P. Walker and S. Ghosh

Session 7C: Analog Design and Layout Tools

Moderators: G. Gielen, Katholieke Universiteit Leuven, Belgium, A. Richardson, University of Lancaster, UK
Analogue Layout Generation by World Wide Web Server-Based Agents [pp 384]
L.T. Walczowski, D. Nalbantis, W.A.J. Waller, and K. Shi

A Performance-Driven Placement Algorithm with Simultaneous Place& Route Optimization for Analog IC’s [pp 389]
J.A. Prieto, A. Rueda, J.M. Quintana, and J.L. Huertas

An Algorithm for Numerical Reference Generation in Symbolic Analysis of Large Analog Circuits [pp 395]
I. García-Vargas, M. Galán, F.V. Fernández, and A. Rodríguez-Vázquez

Session 8A: Embedded Tutorial: Hardware and Software Co-Design in Europe and the USA —- A Collaborative Initiative

Moderator: J.M. Laporte, OMIMO, Belgium
Presenters: D. Gajski, University of California, Irvine, USA, R. Ernst, TU Braunschweig, Germany

Session 8B: Power Modeling and Estimation

Moderators: H. Fleurkens, Philips Research Laboratories, The Netherlands, R. Schlagenhaft, Technical University of Munich, Germany
Adaptive Least Mean Square Behavioral Power Modeling [pp 404]
A. Bogliolo, L. Benini, and G. De Micheli

Fast Power Loss Calculation for Digital Static CMOS Circuits [pp 411]
S. Gavrilov, A. Glebov, S. Rusakov, D. Blaauw, L. Jones, and G. Vijayan

Monte-Carlo Approach for Power Estimation in Sequential Circuits [pp 416]
V. Saxena, F.N. Najm, and I.N. Hajj

Session 8C: Formal Methods in Synthesis and Verification

Moderators: P. Camurati, Politecnico di Torino, Italy, H. Eveking, Technische Hochschule Darmstadt, Germany
Hybrid Symbolic-Explicit Techniques for the Graph Coloring Problem [pp 422]
S. Chiusano, F. Corno, P. Prinetto, and M. Sonza Reorda

A Constructive Approach Towards Correctness of Synthesis - —Application within Retiming [pp 427]
D. Eisenbiegler, R. Kumar, and C. Blumenröhr

A Symbolic Core Approach to the Formal Verification of Integrated Mixed-Mode Applications [pp 432]
S. Hendricx and L. Claesen

Panel P2 - Are There Conflicts of Interest in Intellectual Property Based Business?
Coordinator: I. Bolsens, IMEC, Belgium
Moderator: M. Cecchini, OMI, CEC

Panel:
J. Goria, Italtel, Italy
M. Muller, ARM, UK
R. Lannoo, Alcatel-Mietec, Belgium
A. Wild, Motorola, USA
O. Levia, Cadence, USA
B. Barrera, Mentor Graphics, USA

Session 9B: Concurrent Checking

Moderators: M. Nicolaidis, TIMA, Grenoble, France, L. Bouzaida, SGS Thomson Microelectronics, France
A Novel Methodology for Designing TSC Networks Based on Parity Bit Code [pp 440]
C. Bolchini, F. Salice, and D. Sciuto

Testing Scheme for IC’s Clocks [pp 445]
M. Favalli and C. Metra

A Totally Self-Checking 1-out-of-3 Code Error Indicator [pp 450]
A. Paschalis, N. Gaitanis, D. Gizopoulos, and P. Kostarakis

Session 9C: New Ideas in Scheduling

Moderators: R. Hermida, Universidad Complutense de Madrid, Spain, P. Kission, TIMA, Grenoble, France
Cone-Based Clustering Heuristic for List-Scheduling Algorithms [pp 456]
S. Govindarajan and R. Vemuri

Register Synthesis for Speculative Computation [pp 463]
D. Herrmann and R. Ernst

Multidimensional Periodic Scheduling: A Solution Approach [pp 468]
W.F.J. Verhaegh, P.E.R. Lippens, E.H.L. Aarts and J.L. van Meerbergen

Session 10A: System Level Design Representation and Transformation

Moderators: A. Jerraya, TIMA, Grenoble, France, R. Leupers, University of Dortmund, Germany
Multi-Thread Graph: A System Model for Real-Time Embedded Software Synthesis [pp 476]
F. Thoen, J. Van Der Steen, G. de Jong, G. Goossens, and H. De Man

PCC: A Modeling Technique for Mixed Control/Data Flow Systems [pp 482]
T. Grötker, R. Schoenen, and H. Meyr

Procedure Cloning: A Transformation for Improved System-Level Functional Partitioning [pp 487]
F. Vahid

Session 10B: Diagnosis and Test Generation

Moderators: P. Prinetto, Politecnico di Torino, Italy, C. Landrault, LIRMM, France
A Fault Diagnosis Methodology for the UltraSPARCTM-I Microprocessor [pp 494]
S. Narayanan, R. Srinivasan, R.P. Kunda, M.E. Levitt, and S. Bozorgui-Nesbat

Improved Diagnosis of Realistic Interconnect Shorts [pp 501]
J.T. de Sousa and P.Y.K. Cheung

On Improving Genetic Optimization Based Test Generation [pp 506]
I. Pomeranz and S.M. Reddy

Session 10C: Logic Synthesis for Low Power

Moderators: O. Coudert, Synopsys Inc., USA, K. Antreich, Technical University of Munich, Germany
Symbolic Synthesis of Clock-Gating Logic for Power Optimization of Control-Oriented Synchronous Networks [pp 514]
L. Benini, G. De Micheli, E. Macii, M. Poncino, and R. Scarsi

Low Power FSM Design Using Huffman-Style Encoding [pp 521]
P. Surti, L.F. Cho, and A. Tyagi

Improving the Accuracy of Support-Set Finding Method for Power Estimation of Combinational Circuits [pp 526]
H. Choi and S.H. Hwang

Session 11A: System Design Methodologies

Moderators: L. Nederlof, Philips Semiconductors, The Netherlands, F. Novak, Jozef Stefan Institute Ljubljana, Slovenia
Practical Concurrent ASIC and System Design and Verification [pp 532]
I. Gibson and C. Amies

A Methodology for Hardware Architecture Trade-Off at Different Levels of Abstraction [pp 537]
C. Schneider

Synthesis of Multi-Rate and Variable Rate Circuits for High Speed Telecommunications Applications [pp 542]
P. Schaumont, S. Vernalde, L. Rijnders, M. Engels, and I. Bolsens

Session 11B: Testability at Different Abstraction Levels

Moderators: R. Segers, Philips ED&T, The Netherlands, G. Krampl, Siemens AG, Germany
Testability of 2-Level AND/EXOR Circuits [pp 548]
R. Drechsler, H. Hengster, H. Schäfer, J. Hartmann, and B. Becker

On the Use of Reset to Increase the Testability of Interconnected Finite- State Machines [pp 554]
I. Pomeranz and S.M. Reddy

A New Approach to Build a Low-Level Malicious Fault List Starting from High-Level Description and Alternative Graphs [pp 560]
A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, and R. Ubar

Session 11C: Hardware and Software Tools for Analog and Mixed-Signal Test

Moderators: J.L. Huertas, CNM, Seville, Spain, M. Sachdev, Philips Research, The Netherlands
On-Chip Analog Output Response Compaction [pp 568]
M. Renovell, F. Azaïs, and Y. Bertrand

A New Quality Estimation Methodology for Mixed-Signal and Analogue ICs [pp 573]
T. Olbrich, I.A. Grout, Y. Eben Aimine, A.M. Richardson, and J. Contensou

Compact Structural Test Generation for Analog Macros [pp 581]
V. Kaal and H. Kerkhoff

Session 11D: Power Estimation and Modeling

Moderators: J.L. Conesa, Telefonica I+D, Spain, I. Bolsens, IMEC, Belgium
Accurate High Level Datapath Power Estimation [pp 590]
J.E. Crenshaw and M. Sarrafzadeh

Maximizing the Weighted Switching Activity in Combinational CMOS Circuits Under the Variable Delay Model [pp 597]
S. Manich and J. Figueras

Internal Power Modelling and Minimization in CMOS Inverters [pp 603]
S. Turgis, J.M. Daga, J.M. Portal, and D. Auvergne

Poster Session :

A New Field Programmable System-on-a-Chip for Mixed-Signal Integration [pp 610]
J. Faura, C. Horton, B. Krah, J. Cabestany, M.A. Aguirre, and J.M. Insenser

PROPHID: A Data-Driven Multi-Processor Architecture for High-Performance DSP [pp 611]
J.A.J. Leijten, J.L. van Meerbergen, A.H. Timmer, and J.A.G. Jess

ReCode: The Design and Re-Design of the Instruction Codes for Embedded Instruction-Set Processors [pp 612]
C. Liem, P. Paulin, and A. Jerraya

A Real-Time Smart Sensor System for Visual Motion Estimation [pp 613]
T. Röwekamp and L. Peters

Full Custom Chip Set for High Speed Serial Communications up to 2.48Gbit/s [pp 614]
J. González-Torres, P.A. Mateos, and J.M. Hernández

An Asynchronous Architecture for Digital Signal Processors [pp 615]
M.R. Karthikeyan and S.K. Nandy

Test Synthesis for DC Test of Switched-Capacitors Circuits [pp 616]
H. Ihs and C. Dufaza

SISSSI—A Tool for Dynamic Electro-Thermal Simulation of Analog VLSI Cells [pp 617]
V. Székely, A. Páhi, A. Poppe, M. Rencz, and A. Csendes

Design of Oscillation-Based Test Structures for Active RC Filters [pp 618]
M. Santo Zarnik, F. Novak, and S. Macek

Using Constraint Logic Programming in Memory Synthesis for General Purpose Computers [pp 619]
R. Beckmann and J. Herrmann

Optimal Scheduling for Fast Systolic Array Implementations [pp 620]
I. Ozimek, R. Verlic, and J. Tasic

Scheduling Using Mixed Arithmetic: An ILP Formulation [pp 621]
A. Mignotte and O. Peyran

Performance Verification Using Partial Evaluation and Interval Analysis [pp 622]
J. Walrath, R. Vemuri, and W. Bradley

Design and Verification of the Sequential Systems Automata Using Temporal Logic Specifications [pp 623]
A. Ursu, G. Gruita, and S. Zaporojan

Application Independent Module Generation in Analog Layouts [pp 624]
M. Wolf and U. Kleine

A Scheme for Multiple On-Chip Signature Checking for Embedded SRAMs [pp 625]
M.F. Abdulla, C.P. Ravikumar, and A. Kumar

Design of Partially Parallel Scan Chain [pp 626]
Y. Higami and K. Kinoshita

March LA: A Test for Linked Memory Faults [pp 627]
A.J. van de Goor, G.N. Gaydadjiev, V.N. Yarmolik, and V.G. Mikitjuk

The Input Pattern Fault Model and Its Application [pp 628]
R.D. Blanton and J.P. Hayes

A Monolithic Off-Chip IDDQ Monitor [pp 629]
M. Svajda, B. Straka, and H. Manhaeve

Extension of the Boundary-Scan Architecture and New Idea of BIST for More Effective Testing and Self-Testing of Interconnections [pp 630]
A. Kristof