Technical Reports

R. Jejurikar and R. Gupta, "Procrastination Scheduling in Fixed Priority Real-Time Systems," TR 04-09, April, 2004. download pdf

D. Shin, A. Gerstlauer, R. Doemer, D. Gajski, "System-on-Chip Communication Modeling Style Guide," TR 04-25, July 2004. download pdf

M. Reshadi and D. Gajski, "NISC Modeling and Simulation," TR 04-08, March 2004. download pdf

D. Shin, L. Cai, A. Gerstlauer, R. Doemer, D. Gajski, "System-on-Chip Transaction-Level Modeling Style Guide," TR 04-24, July 2004. download pdf

N. Savoiu, S. Shukla, and R. Gupta, "A Semantics-Preserving Reduction of Code-Annotated Well-formed Free Choice Petri Nets," TR 04-07, February 12, 2004. download pdf

D. Shin, J. Peng, A. Gerstlauer, R. Doemer, D. Gajski, "System-On-Chip Network Modeling Style Guide," TR 04-23, July 31, 2004. download pdf

S. Pasricha, M. Ben-Romdhane, and N. Dutt, "High Level Design Space Exploration of Shared Bus Communication Architectures," TR 04-06, March 13, 2004. download pdf

J. Peng, A. Gerstlauer, R. Doemer, D. Gajski, "System-On-Chip Architecture Modeling Style Guide," TR 04-22, July 31, 2004. download pdf

P. Biswas, S. Banerjee, N. Dutt, L. Pozzi, P. Ienne, "ISEGEN: Adapting Kernighan-Lin Min-Cut Heuristic for Generation of Instruction Set Extensions," TR 04-21, August 12, 2004. download pdf

P. Mishra and N. Dutt, "Functional Coverage Driven Test Generation for Validation of Pipelined Processors," TR 04-05, March 12, 2004. download pdf

S. Pasricha, N. Dutt, and M. Ben-Romdhane, " Automated Synthesis of Bus Architectures for Systems with Throughput Constraints," TR 04-20, August 2004. download pdf

L. Cai, A. Gerstlauer, and D. Gajski, "Retargetable Profiling for Rapid, Early System-Level Design Space Exploration," TR 04-04, February 2004. download pdf

R. Doemer, A. Gerstlauer, D. Shin, "Cycle-accurate RTL Modeling with Multi-Cycled and Pipelined Components," TR 04-19, July 22, 2004. download pdf

R. Jejurikar and R. Gupta, "Integrating Processor Slowdown and Preemption Threshold Scheduling for Energy Efficiency in Real Time Embedded Systems," TR 04-03, February 16, 2004. download pdf

S. Banerjee and N. Dutt, "Very Fast Simulated Annealing for HW-SW Partitioning," TR 04-18, June 2004. download pdf

J. Trajkovic and A. Veidenbaum, "Reducing SDRAM Energy Consumption in Embedded Systems," TR 04-02, October 2004. download pdf

P. Chandraiah, H. Schirner, N. Srinivas, and R. Doemer, "System-On Chip Modeling and Design: A Case Study on MP3 Decoder," TR 04-17, June 21, 2004. download pdf

R. Jejurikar and R. Gupta, "Energy Aware Non-preemptive Scheduling for Hard Real-Time Systems," TR 04-01, January 21, 2004. download pdf

M. Reshadi and D. Gajski, “NISC Modeling and Compilation,” TR 04-33, December 2004. download pdf

D. Shin, A. Gerstlauer, and D. Gajski, “Communication Link Synthesis for SoC,” TR 04-16, June 10, 2004. download pdf

A. Gupta and R. Doemer, "System Design of Digital Camera Using SpecC," TR 04-32, December 10, 2004. download pdf

D. Shin, A. Gerstlauer, and D. Gajski, "Network Synthesis for SoC," TR 04-15, June 10, 2004. download pdf

R. Jejurikar and R. Gupta, "Leakage Aware Dynamic Slack Reclamation in Real-Time," TR 04-31, November 2004. download pdf

R. Jejurikar and R. Gupta, "Systemwide Energy Minimization in Real-Time Embedded Systems," TR 04-14, May 2004. download pdf

A. Nacul and T. Givargis, "The Phantom Serializing Compiler," TR 04-30, November 22, 2004. download pdf

I. G. Harris, "On the Detection of Synchronization Errors," TR 04-13, May 2004. download pdf

S. Abdi and D. Gajski, "System Level Verification with Model Algebra," TR 04-29, November 9, 2004. download pdf

D. Gajski and M. Reshadi, "NISC Application and Advantages," TR 04-12, May 2004. download pdf

M. Mamidipaka and N. Dutt, "eCACTI: An Enhanced Power Estimation Model for On-chip Caches," TR 04-28, September 14, 2004. download pdf

S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Rapid Exploration of Bus-based Communication Architectures at the CCATB Abstraction," TR 04-11, May 2004. download pdf

B. Gorjiara, P. Chou, N. Bagherzadeh, "An Algorithm to Avoid Power Command Jitter in Middleware-Based Distributed Embedded Systems," TR 03-47, July 2003. download pdf

N. Bansal, S. Gupta, N. Dutt, A. N, and R. Gupta, "Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures," TR03-27, August 2003. download pdf

D. D. Gajski and L. Cai, "Transaction Level Modeling in System Level Design," TR 03-10, March 28, 2003. download pdf

B. Gorjiara, F. Kuester, P. Chou, and M. Reshadi, "GX-GUI: A General Extensible Technique for 2-D Interaction with VR Applications," TR 03-46, January 2003. download pdf

A. Gerstlauer, L.Cai, D. Shin, R. Doemer, and D. Gajski, "System-On-Chip Component Models," TR 03-26, August 11, 2003. Complete TR is available upon request

D. D. Gajski, A. Tripathi, and S. Verma, "G.729E Algorithm Optimization for ARM926EJ-S Processor," TR 03-09, March 21, 2003. download pdf

L. Cai, A. Gerstlauer, S. Abdi, J. Peng, D. Shin, H. Yu, R. Doemer, D. Gajski, "System-on-Chip Environment (SCE Version 2.2.0 Beta): Manual," TR 03-45, December 2003. download pdf

D. Shin, A. Gerstlauer, R. Doemer, and D. Gajski, "C-based Interactive RTL Design Methodology," TR 03-42, December 1, 2003. download pdf

P. Mishra, N. Dutt and H. Tomiyama, "Architecture Description Language driven Validation of Dynamic Behavior in Pipelined Processor Specifications," TR 03-25, July 28, 2003. download pdf

D. D. Gajski and S. Abdi, "Automatic Communication Refinement for System Level Design," TR 03-08, March 7, 2003. download pdf

S. Abdi, J. Peng, H. Yu, D. Shin, A. Gerstlauer, R. Doemer, and D. Gajski, "System-on-Chip Environment: SCE Version 2.2.0 Beta Tutorial," TR 03-41, December 2003. download pdf

S. Pasricha and A. Veidenbaum, "Novel Techniques to Improve Branch Prediction Accuracy for Embedded Processors in the Presence of Context Switches," TR 03-24, August 2003. download pdf