Books and Book Chapters
The Compiler Design Handbook: Optimizations and Machine Code Generation
Mall, Rajib, Y. N. Srikant, Priti Shankar, Uday Khedker, K. Gopinath, Sharad Malik, R. Govindarajan, Sanjay Rajopadhye, Evelyn Duesterwald, Rajiv Gupta, Robert Nigel Horspool, Ganga Bishnu Mund, Thomas Reps, Mooly Sagiv, Neelam Gupta, Andreas Krall, David August, Nikil Dutt, Amitabha Sanyal, Tulika Mitra, Abhik Roychoudhury, Aviral Shrivastava, Xiangyu Zhang, Easwaren Raman, K Anada Vardhan, Kapil Vaswani, P. J. Joseph, Mathew T. Jacob, Jens Palsberg, Todd Millstein, J Prakash Prabhu, Reinhard Wilhelm, Lakshminarayann Renganarayana, Gautam Gupta, Michelle Strout, Wei Qin, Subramanian Rajagopalan, Hongbo Rong, V Krishna Nandivada. “The Compiler Design Handbook: Optimizations and Machine Code Generation”, 2018
Avery, M.C. and Krichmar. Models of Neuromodulation in Computational Models of Brain and Behavior
Avery, M.C. and Krichmar, J.L. Models of Neuromodulation in Computational Models of Brain and Behavior. A. Moustafa, Editor, John Wiley & Sons Limited, November 2017
Computational Models of Brain and Behavior
Avery, M. C., & Krichmar, J. L. (2017). Models of neuromodulation. Computational Models of Brain and Behavior, 373-388.
Processor Modeling and Design Tools. Electronic Design Automation for IC System Design, Verification, and Testing
Chattopadhyay, Anupam, Nikil Dutt, Rainer Leupers, and Prabhat Mishra. (2017). Processor Modeling and Design Tools. Electronic Design Automation for IC System Design, Verification, and Testing, pp. 121-140.
Handbook of Hardware/Software Codesign
Park, Young Hwan, Amin Khajeh, Jun Yong Shin, Fadi Kurdahi, Ahmed Eltawil, and Nikil Dutt. (2017) Microarchitecture-level SoC design. In Handbook of Hardware/Software Codesign. Pp. 867-913. Springer Netherlands.
Handbook of Hardware/Software Codesign
Park, Young Hwan, Amin Khajeh, Jun Yong Shin, Fadi Kurdahi, Ahmed Eltawil, and Nikil Dutt. (2017). Microarchitecture-level SoC design. Handbook of Hardware/Software Codesign. Springer Netherlands. pp. 867-913.
Handbook of Hardware/Software Codesign
Ha, Soonhoi, Jürgen Teich, Christian Haubelt, Michael Glaß, Tulika Mitra, Rainer Dömer, Petru Eles, Aviral Shrivastava, Andreas Gerstlauer, and Shuvra S. Bhattacharyya. (2017) “Introduction to hardware/software codesign.” Handbook of Hardware/Software Codesign, 3-26.
Handbook of Hardware/Software Codesign
Schirner, Gunar, Andreas Gerstlauer, and Rainer Dömer. (2017). “SCE: System-on-Chip Environment.” In Handbook of Hardware/Software Codesign, pp. 1019-1050. Springer, Dordrecht.
Handbook of Hardware/Software Codesign
Dömer, Rainer, Guantao Liu, Tim Schmidt, S. Ha, and J. Teich. (2017). “Parallel Simulation.” Handbook of Hardware/Software Codesign, pp. 533-564.
Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion
Elsharkasy, Wael M., Hasan Erdem Yantir, Amin Khajeh, Ahmed M. Eltawil, and Fadi J. Kurdahi. (2017). Efficient pulsed-latch implementation for multiport register files: work-in-progress. Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, pp. 1-2.
Handbook of Hardware/Software Codesign
Sarma, Santanu, and Nikil Dutt. (2017). Architecture and Cross-Layer Design Space Exploration. In Handbook of Hardware/Software Codesign, pp. 247-270.
Proceedings of the International Conference on Research in Adaptive and Convergent Systems
Chi-Sheng Shih, Tim-Yuao Wang, Jyun-Jhe Chou, Ze-Yu Chuang, Ching-Chi Chuang, Kwei-Jay Lin, Wei-Dean Wang, Kuo-Chin Huang (2017). Collaborative sensing for privacy preserving gait tracking using IoT middleware. In Proceedings of the International Conference on Research in Adaptive and Convergent Systems, pp. 152-159.
Per Larsen, Stefan Brunthaler, Lucas Davi, Ahmad-Reza Sadeghi, and Michael Franz, Automated Software Diversity
Per Larsen, Stefan Brunthaler, Lucas Davi, Ahmad-Reza Sadeghi, and Michael Franz, Automated Software Diversity, Morgan & Claypool Publishing, December 2015
Michael T. Goodrich, Roberto Tamassia, Algorithm Designs and Applications
Michael T. Goodrich, Roberto Tamassia, Algorithm Designs and Applications, Wiley, October 2015
Michael T. Goodrich, Roberto Tamassia, Michael H. Goldwasser, Data Structures and Algorithms in Java 6/e
Michael T. Goodrich, Roberto Tamassia, Michael H. Goldwasser, Data Structures and Algorithms in Java 6/e, Wiley, January 2014
Vipul Jain and Payam Heydari, Automotive Sensors in Silicon Technologies, Springer Verlag Publishing, 2013
Vipul Jain and Payam Heydari, Automotive Radar Sensors in Silicon Technologies, Spring Verlag Publishing, 2013
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D. D. Gajski, S. Abdi, A. Gerstlauer, and G. Schirner, Embedded System Design: Modeling, Synthesis, Verification
Embedded System Design: Modeling, Synthesis, Verification
Embedded System Design: Modeling, Synthesis, Verification presents information on how to design a future multiprocessor system consisting of several processors and other components. Design methodology, modeling techniques, software and hardware synthesis methods and techniques for verification of such multi-processor systems are also discussed. The authors provide model based system synthesis techniques, including algorithms for platform design and application to platform design and application to platform mapping in addition to introducing methodology, design and tool concepts and delving into modeling practice and requirements all the way from application specification to system prototyping. Embedded System Design, authored by Daniel Gajski, Samar Abdi, Andreas Gerstlauer, and Gunar Schirner, is written for embedded system designers, instructors, and graduate students.
View book review by IEEE Design & Test of Computers
Chapter 1: Introduction (pdf)
View video – Processor Level Design
View video – System Level Design
View video – System Level Status
View video – System Level Future
Chapter 2: System Design Methodologies (pdf)
View video – System Design Methodologies
Chapter 3: Modeling (pdf)
View video – Models of Computation
View video – System Design
View video – Processor Modeling
View video – Communication Modeling
Chapter 4: System Synthesis (pdf) (errata)
View video – System Design Trends and Model Based Synthesis
View video – Transaction Level Model Generation
View video – Application to Platform Mapping
View video – Platform and Cycle-Accurate Model Generation
Chapter 5: Software Synthesis (pdf)
View video – Software Synthesis Introduction
View video – Code Generation
View video – Hardware-dependent Software (Part 1)
View video – Hardware-dependent Software (Part 2)
View video – Hardware-dependent Software (Part 3)
Chapter 6: Hardware Synthesis (pdf)
View video – Specification and Architecture
View video – High-level Synthesis
View video – Chaining and Pipelining
View video – Scheduling and Interfacing
Chapter 7: Verification (pdf)
View video – Simulation and Debugging Methods
View video – Formal Verification Methods
View video – Comparative Analysis of Verification Techniques
View video – Model Formalization for SoC Verification
Chapter 8: Embedded Design Practice (pdf)
Transaction Level Model Automation for Multicore Systems
Yu Lo, S. Abdi, D. Gajski, “Transaction Level Model Automation for Multicore Systems” in Behavioral Modeling for Embedded Systems and Technologies (Gomes and Fernandes, eds), IGI Global, Hershey, Pennsylvania, 2009
Transaction-Level System Modeling
Daniel Gajski and Samar Abdi, “Transaction-Level System Modeling”, in Practical Design Verification (D. K. Pradhan and I. G Harris, eds), Cambridge University Press, 2009
Hardware-dependent Software – Introduction and Overview
W. Ecker, W. Mueller, R. Doemer, “Hardware-dependent Software – Introduction and Overview,” Chapter 1 in Hardware-dependent Software: Principles and Practice (ed. W. Ecker, W. Müller, R. Dömer), Springer, Boston, January 2009. (ISBN 978-1-4020-9435-4)
W. Ecker, W. Mueller, R. Doemer, Hardware-dependent Software – Principles and Practice
W. Ecker, W. Mueller, R. Doemer, Hardware-dependent Software – Principles and Practice. Springer, Boston, January 2009.
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A Partial Memory Protection Scheme for Higher Effective Yield of Embedded Memory for Video Data
Kang Yi, Shih-Yang Cheng, Fadi Kurdahi and Ahmed Eltawil, “A Partial Memory Protection Scheme for Higher Effective Yield of Embedded Memory for Video Data” Accepted to Advances in Computer Systems Architecture , Springer Publishers, 2008. ( PDF )
Sudeep Pasricha, Nikil Dutt. On-Chip Communication Architectures: System on Chip Interconnect
Web Site : http://www.engr.colostate.edu/~sudeep/research/book_comm.htm
· Definitive guide to on-chip communication architectures for emerging chip multi-processor systems
· Detailed analysis of all popular standards for on-chip communication
· Comprehensive survey of research on communication architectures, covering a wide range of topics, spanning the past several years and up to date with the most current research
· Overview of future trends that will have a significant impact on communication architecture research and design over the next several years: networks-on-chip, optics, wireless, 3D, carbon nanotube on-chip interconnects
Introduction: System Level Design: Past, Present and Future
D. Gajski, “Introduction: System Level Design: Past, Present and Future”, Lauwereins, Rudy; Madsen, Jan (Editors) Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE, Springer, ISBN: 978-1-4020-6487-6, March 2008
An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories
Kang Yi, Shih-Yang Cheng, Young-Hwan Park, Fadi Kurdahi and Ahmed Eltawil, “An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories,” Advances in Computer Systems Architecture, Springer Publishers, Vol. 4697, 2007. ( PDF )
An Interactive Design Environment for C-Based High-Level Synthesis
D. Shin, A. Gerstlauer, R. Doemer, and D. Gajski, “An Interactive Design Environment for C-Based High-Level Synthesis,” in Embedded Systems Design: Topics, Techniques, and Trends (A. Rettenberg et al, eds), Springer, May 2007
Low-Power Design with NISC Technology
B. Gorjiara, M. Reshadi, D. Gajski, “Low-Power Design with NISC Technology”, J. Henkel, S. Parameswaran, Designing Embedded Processors: A Low Power Perspective, Springer, ISBN: 978-1-4020-5868-4, April 2007.
Frank Vahid and Roman Lysecky, VHDL for Digital Design
Frank Vahid and Roman Lysecky, VHDL for Digital Design, WIley, ISBN 978-0470052631, March 2007.
Website
Design and Analysis of Low Power Image Filters toward Defect-Resilient Embedded Memories for Multimedia SoCs
Y. Kang, K. Jung, S. Cheng, Y. Park, F. Kurdahi, A. Eltawil : Design and Analysis of Low Power Image Filters toward Defect-Resilient Embedded Memories for Multimedia SoCs 11th Asia-Pacific Computer System Architecture Conference (ACSAC 2006). pp. 295-308.
Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs
Kang Yi, Kyeong Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi Kurdahi and Ahmed Eltawil, “Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs,” Advances in Computer Systems Architecture, Springer Publishers, Vol. 4186, 2006. ( PDF )
Software and Driver Synthesis from Transaction level Models
H. Yu, R. Doemer and D. D. Gajski, “Software and Driver Synthesis from Transaction level Models,” Specification to Embedded System Application (Rettberg, Zanella, Rammig, eds.) Springer, 2005, pp. 65-76
A Scalable Embedded JPEG2000 Architecture Lecture Notes
C. Zhang, Y. Long, F. Kurdahi: A Scalable Embedded JPEG2000 Architecture Lecture Notes in Computer Science (Springer-Verlag) Vol 3553/2005. 5th Intl Workshop SAMOS 2005. p 334. 2005.
Automatic Generation of Communication Architectures
D. Shin, A. Gerstlauer, R. Doemer and D. D. Gajski, “Automatic Generation of Communication Architectures,” From Specification to Embedded System Application (Rettberg, Zanella, Rammig, eds.) Springer, August 2005, pp. 179-188.
Prabhat Mishra and Nikil D. Dutt, Functional Verification of Programmable Embedded Architectures: A Top-Down Approach
Prabhat Mishra and Nikil D. Dutt, Functional Verification of Programmable Embedded Architectures: A Top-Down Approach, ISBN 978-0-387-26143-0, 2005.
Website
Reconfigurable DSP Platforms
B. Mohebbi, F. Kurdahi: Reconfigurable DSP Platforms In Software-Defined Radio: Baseband for Cellular Technologies, John Wiley & Sons. 2004.
Sudeep Gupta, Nikil Dutt, Rajesh Gupta, and Alex Nicolau. SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits
SPARK: A Parallelizing Approach to the High – Level Synthesis of Digital Circuits
Review from Kluwer
Web Site: http://mesl.ucsd.edu/spark/
Rapid advances in microelectronic integration and the advent of Systems-on-Chip have fueled the need for high-level synthesis, i.e., an automated approach to the synthesis of hardware from behavioral descriptions.
SPARK: A Parallelizing Approach to the High – Level Synthesis of Digital Circuits presents a novel approach to the high-level synthesis of digital circuits — that of parallelizing high-level synthesis (PHLS). This approach uses aggressive code parallelizing and code motion techniques to discover circuit optimization opportunities beyond what is possible with traditional high-level synthesis. This PHLS approach addresses the problems of the poor quality of synthesis results and the lack of controllability over the transformations applied during the high-level synthesis of system descriptions with complex control flows, that is, with nested conditionals and loops.
Also described are speculative code motion techniques and dynamic compiler transformations that optimize the circuit quality in terms of cycle time, circuit size and interconnect costs. We describe the SPARK parallelizing high-level synthesis framework in which we have implemented these techniques and demonstrate the utility of SPARK’s PHLS approach using designs derived from multimedia and image processing applications. We also present a case study of an instruction length decoder derived from the Intel Pentium-class of microprocessors. This case study serves as an example of a typical microprocessor functional block with complex control flow and demonstrates how our techniques are useful for such designs.
SPARK: A Parallelizing Approach to the High – Level Synthesis of Digital Circuits is targeted mainly to embedded system designers and researchers. This includes people working on design and design automation. The book is useful for researchers and design automation engineers who wish to understand how the main problems hindering the adoption of high-level synthesis among designers.
Aminghasem Safarian and Payam Heydari, Silicon-Based RF Front-Ends for Ultra Wideband Radios
Aminghasem Safarian and Payam Heydari, Silicon-Based RF Front-Ends for Ultra Wideband Radios, Spring-Verlag New York, LLC, January 2008
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C/C++ Based System Design Flow Using SpecC, VCC, and SystemC
L. Cai, M. Olivarez, P. Kritzinger, and D. D. Gajski, “C/C++ Based System Design Flow Using SpecC, VCC, and SystemC,” System Specification and Design Languages, edited by E Villar, Kluwer Academic Publishers, Boston, 2003.
RTOS Modeling for System-Level Design
A. Gerstlauer, H. Yu and D. D. Gajski, “RTOS Modeling for System-Level Design,” Embedded Software for SoC, edited by A. A. Jerraya, S. Yoo, N. When, D. Verkest, Kluwer Academic Publishers, June 2003.
Peter Grun, Nikil Dutt, and Alex Nicolau. Memory Architecture Exploration for Programmable Embedded Systems
Memory Architecture Exploration for Programmable Embedded System
Editorial Review from Book News, Inc.
This book presents a “compiler-in-the-loop” exploration strategy for alternative memory architectures, allowing for effective matching of the target application to the processor-memory architecture. This new approach for memory architecture exploration replaces the traditional black-box view of the memory system. The utility of the approach is illustrated for a set of large, real-life benchmarks. Material is of interest to different groups in the embedded systems-on-chip field, including researchers and students in memory architecture, CAD developers, and system designers. Grun is affiliated with the Center for Embedded Computer Systems, University of California-Irvine.
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