Embedded System Design: Modeling, Synthesis, Verification Ch 7: Model Formalization for SoC Verification October 19, 2012 Post navigation Previous Previous post: Embedded System Design: Modeling, Synthesis, Verification Ch 7: Comparative Analysis of Verification TechniquesNext Next post: Embedded System Design: Modeling, Synthesis, Verification Ch 8: Embedded System Environment (ESE) Case Study
