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Conference Proceedings

Design, Automation and Test in Europe Conference (DATE ‘04)

Location: Paris, France
Web Site: http://www.date-conference.com/

J. Aragon, D. Nicolaescu, A. Veidenbaum, and A. Badulescu, “Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1374-1375, February 16-20, 2004

B. Arslan and A. Orailoglu, “Circular-Scan: A Scan Architecture for Test Cost Reduction,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1290-1295, February 16-20, 2004

N. Bansal, S. Gupta, N. Dutt, A. Nicolau, and R. Gupta, “Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 474-479, February 16-20, 2004

A. Gordon-Ross, F. Vahid, and N. Dutt, “Automatic Tuning of Two-Level Caches to Embedded Applications,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 208-213, February 16-20, 2004

S. Gupta, N. Dutt, A. Nicolau, and R. Gupta, “Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 114-120, February 16-20, 2004

M. Heath, W. Burleson, and I. G. Harris, “Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC,” IEEE/ACM Design Automation and Test in Europe Conference (DATE ’04), Paris, France, February 16-20, 2004 download pdf

R. Lysecky, and F. Vahid, “A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 480-485, February 16-20, 2004

P. Mishra, N. Dutt, “Graph-Based Functional Test Program Generation for Pipelined Processors,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 182-187, February 16-20, 2004

A. Nacul and T. Givargas, “Dynamic Voltage and Cache Reconfiguration for Low Power,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1376-1378, February 16-20, 2004

O. Sinanoglu and A. Orailoglu, “Scan Power Minimization Through Stimulus and Response Transformations,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 404-409, February 16-20, 2004

C. Zhang and F. Vahid, “Using a Victim Buffer in an Application-Specific Memory Hierarchy,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 220-227, February 16-20, 2004

C. Zhang, F. Vahid, and R. Lysecky, “A Self-Tuning Cache Architecture for Embedded Systems,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 142-147, February 16-20, 2004

C. Zhang, J. Yang, and F. Vahid, “Low Static-Power Frequent-Value Data Caches,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 214-219, February 16-20, 2004

Asia South Pacific Design Automation Conference 2004 Pacifico Yokohama (ASP-DAC 2004)

Location: Yokohama, Japan
Web Site: http://www.aspdac.com/

S. Abdi and D. Gajski, “On Deriving Equivalent Architecture Model from System Specification,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 322-327, January 27-30, 2004

L. Cai, H. Yu and D. Gajski, “A Novel Memory Size Model for Variable-Mapping in System Level Design,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 813-818, January 27-30, 2004

B. Gorji-Ara, P. Chou, N. Bagherzadeh, M. Reshadi and D. Jensen, “Fast and Efficient Voltage Scheduling by Evolutionary Slack Distribution,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 659-662, January 27-30, 2004

P. Heydari, “High-Frequency Noise in RF Active CMOS Mixers,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 57-61, January 27-30, 2004 download pdf

D. Shin, S. Abdi, and D. Gajski, “Automatic Generation of Bus Functional Models from Transaction Level Models,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 756-758, January 27-30, 2004

A. Shrivastava and N. Dutt, “Energy Efficient Code Generation Exploiting Reduced Bit-Width Instruction Set Architectures (rISA),”Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 475-477, January 27-30, 2004

O. Sinanoglu and A. Orailoglu, “Efficient RT-Level Fault Diagnosis Methodology,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 212- 217, January 27-30, 2004

R. Topaloglu and A. Orailoglu, “On Mismatch in the Deep Sub-Micron Era – From Physics to Circuits,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 62-67, January 27-30, 2004

H. Yu, R. Doemer and D. Gajski, “Embedded Software Generation from System-Level Design Languages,” Asia and South Pacific Design Automation Conference (ASP-DAC 2004), Yokohama, Japan, pp 463-468, January 27-30, 2004

IEEE International Symposium on Circuits and Systems (ISCAS 2004)

Location: Vancouver, Canada
Web Site: http://www.iscas2004.org/

A. Yazdi and P. Heydari, “A Novel Non-Uniform Distributed Amplifier,” to appear in IEEE International Symposium on Circuits and Systems, May 23-26, 2004.

A. Safarian and P. Heydari, “Design and and Analysis of a Distributed Regenerative Frequency Divider Using a Distributed Mixer,” to appear in IEEE International Symposium on Circuits and Systems, May 23-26, 2004.

Ravindran Mohanavelu and Payam Heydari, “A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider,” to appear in IEEE International Symposium on Circuits and Systems, May 23-26, 2004.

Design Automation Conference 2004 (DAC 2004)

Location: San Diego, CA
Web Site: http://www.dac.com/

S. Abdi and D. Gajski, “Automatic Generation of Equivalent Architecture Model from Functional Specification,” Design and Automation Conference (DAC 2004), pp 608-613, June 7-11, 2004 download pdf

P. Biswas, V. Choudhary, K. Atasu, L. Pozzi, P. Ienne, and N. Dutt, “Introduction of Local Memory Elements in Instruction Set Extensions,” Design and Automation Conference (DAC 2004), pp 729-734, June 7-11, 2004 download pdf
L. Cai, A. Gerstlauer, and D. Gajski, “Retargetable Profiling for Rapid, Early System-Level Design Space Exploration,” Design and Automation Conference (DAC 2004), pp 281-286, June 7-11, 2004

R. Jejurikar, C. Pereira, and R. Gupta, “Leakage Aware Dynamic Voltage Scaling for Real-Time Embedded Systems,” Design and Automation Conference (DAC 2004), pp 275-280, June 7-11, 2004

A. Kejariwal, S. Gupta, A. Nicolau, N. Dutt and R. Gupta, “Proxy-Based Task Partitioning of Watermarking Algorithms for Reducing Energy Consumption in Mobile Devices,” Design and Automation Conference (DAC 2004), pp 556-561, June 7-11, 2004 download pdf

R. Lysecky, F. Vahid, and S. Tan, “Dynamic FPGA Routing for Just-in-Time FPGA Compilation,” Design and Automation Conference (DAC 2004), pp 659-662, June 7-11, 2004 download pdf

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration,” Design and Automation Conference (DAC 2004), pp 113-118, June 7-11, 2004 download pdf

International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004)

Location: Stockholm, Sweden
Web Site: http://www.codes-isss.org/

S. Banerjee and N. Dutt, “Efficient Search Space Exploration for HW-SW Partitioning,” CODES+ISSS 2004, Stockholm, Sweden, pp 122-127, September 8-10, 2004 download pdf

M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir, ” Analytical Models for Leakage Power Estimation of Memory Array Structures,” CODES+ISSS 2004,”Stockholm, Sweden, pp 146-151, September 8-10, 2004 download pdf

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Fast Exploration of Bus-based On-chip Communication Architectures,” CODES+ISSS 2004, Stockholm, Sweden, pp 242-247, September 8-10, 2004 download pdf

F. Rivera, M. Sanchez-Elez, M. Fernandez, R. Hermida, and N. Bagherzadeh, “Efficient Mapping of Hierarchical Trees on Coarse-Grain Reconfigurable Architectures,” CODES+ISSS 2004, Stockholm, Sweden, pp 30-35, September 8-10, 2004 download pdf

A. Shrivastava, E. Earlie, N. Dutt, and A. Nicolau, “Operation Tables for Scheduling in the Presence of Incomplete Bypassing,” CODES+ISSS 2004, Stockholm, Sweden, pp 194-199, September 8-10, 2004 download pdf

14th IEEE Workshop on Rapid System Prototyping

P. Mishra, A. Kejariwal, and N. Dutt, “Rapid Exploration of Pipelined Processors Through Automatic Generation of Synthesizable RTL Models,” 14th IEEE Workshop on Rapid System Prototyping, pp 226-232, San Diego, CA, June 2003

2003 International Symposium on Low Power Electronics and Design

P. Chou, C. Park, J. Park, K. Pham, and J. Liu, “B#: a Battery Emulator and Power Profiling Instrument,” 2003 International Symposium on Low Power Electronics and Design, pp 288-293, Seoul, Korea, August 2003 download pdf

P.Heydari and Y. Zhang, “A Novel High Frequency, High-Efficiency, Differential Class-E Power Amplifier in 0.18um CMOS, Payam Heydari, and Ying Zhang,” 2003 International Symposium on Low Power Electronics and Design, pp 455-458 Seoul, Korea, August 2003 download pdf

J. Lee, K. Choi, and N. Dutt, “Energy-Efficient Instruction Set Synthesis for Application-Specific Processors,” 2003 International Symposium on Low Power Electronics and Design, pp 330-333, Seoul, Korea, August 2003download pdf

D. Nicolaescu, A. Veidenbaum, and A. Nicolau, “Reducing Data Cache Energy Consumption via Cached Load/Store Queue,” 2003 International Symposium on Low Power Electronics and Design, pp 252-257, Seoul, Korea, August 2003 download pdf