Conference Proceedings

D. Li, P. Chou, and N. Bagherzadeh, “Mode Selection and Mode Dependency Modeling for Power-Aware Embedded Systems,” 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002), pp 697-704, Bangalore, India, January 2002 download pdf

P. Mishra, H. Tomiyama, A. Halambi, P. Grun, N. Dutt, and A. Nicolau, “Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language,” 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002), pp 458-463, Bangalore, India, January 2002 download pdf

J. Peng, S. Abdi, and D. Gajski, “Automatic Model Refinement for Fast Architecture Exploration,” 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002), pp 332-337, Bangalore, India, January 2002 download pdf

B. Grattan, G. Stitt, and F. Vahid, “Codesign-Extended Applications,” 10th International Symposium on Hardware/Software CoDesign, pp 1-6, Estes Park, CO, May 2002 download pdf

J. Liu, P. Chou, and N. Bagherzadeh, “Communication Speed Selection for Embedded Systems with Networked Voltage-Scalable Processors,” 10th International Symposium on Hardware/Software CoDesign, pp 169-174, Estes Park, CO, May 2002 download pdf

M. Palesi and T. Givargis, “Multi-Objective Design Space Exploration Using Genetic Algorithms,” 10th International Symposium on Hardware/Software CoDesign, pp 67-72, Estes Park, CO, May 2002 download pdf

P. Petrov and A. Orailoglu, “Energy Frugal Tags in Reprogrammable I-Caches for Application-Specific Embedded Processors,” 10th International Symposium on Hardware/Software CoDesign, pp 181-186, Estes Park, CO, May 2002 download pdf

S. Gupta, T. Kam, S. Rotem, N. Savoiu, N. Dutt, R. Gupta, and A. Nicolau, “Coordinated Transformations for High-Level Synthesis of High Performance Microprocessor Blocks,” 39th Design Automation Conference, pp 898-903, New Orleans, LA, June 2002 download pdf

R. Lysecky, S. Cotterell, and F. Vahid, “A Fast On-Chip Profiler Memory,” 39th Design Automation Conference, pp 28-33, New Orleans, LA, June 2002 download pdf

S. Cotterell and F. Vahid, “Tuning of Loop Cache Architectures to Programs in Embedded System Designs,” International Symposium on System Synthesis, pp 8-13, Kyoto, Japan, October 2002 download pdf

A. Gerstlauer and D. Gajski, “System-Level Abstraction Semantics,” International Symposium on System Synthesis, pp 231-236, Kyoto, Japan, October 2002 download pdf

S. Gupta, M. Reshadi, N. Saviou, N. Dutt, and A. Nicolau, “Dynamic Common Sub-Expression Elimination During Scheduling in High-Level Synthesis,” International Symposium on System Synthesis, pp 261-266, Kyoto, Japan, October 2002 download pdf

J. Liu, P. H. Chou, and N. Bagherzadeh, “Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors,” International Symposium on System Synthesis, pp 14-19, Kyoto, Japan, October 2002 download pdf

M. Mamidipaka, N. Dutt, and D. Hirschberg, “Efficient Power Reduction Techniques for Time Multiplexed Address Buses,” International Symposium on System Synthesis, pp 207-212, Kyoto, Japan, October 2002 download pdf

W. Mueller, R. Doemer, and A. Gerstlauer, “The Formal Execution Semantics of SpecC,” International Symposium on System Synthesis, pp 150-155, Kyoto, Japan, October 2002 download pdf

J. Peng and D. Gajski, “Optimal Message Passing for Data Coherency in Distributed Architecture,” International Symposium on System Synthesis, pp 20-25, Kyoto, Japan, October 2002 download pdf

P. Petrov and A. Orailoglu, “Low-Power Data Memory Communication for Application-Specific Embedded Processors,” International Symposium on System Synthesis, pp 219-224, Kyoto, Japan, October 2002 download pdf

N. Saviou, S. K. Shukla, and R. Gupta, “Efficient Simulation of Synthesis-Oriented System Level Designs,” International Symposium on System Synthesis, pp 168-173, Kyoto, Japan, October 2002 download pdf

S. Cotterell and F. Vahid, “Synthesis of Customized Loop Caches for Core-Based Embedded Systems,” IEEE/ACM International Conference on Computer-Aided Design, pp 655-662, San Jose, CA, November 2002 download pdf

J. Lee, K. Choi, and N. Dutt, “Efficient Instruction Encoding for Automatic Instruction Set Design of Configurable ASIPS,” IEEE/ACM International Conference on Computer-Aided Design, pp 649-654, San Jose, CA, November 2002 download pdf

O. Sinanoglu and A. Orailoglu, “A Novel Scan Architecture for Power-Efficient, Rapid Test,” IEEE/ACM International Conference on Computer-Aided Design, pp 299-303, San Jose, CA, November 2002 download pdf

G. Stitt and F. Vahid, “Hardware/Software Partitioning of Software Binaries,” IEEE/ACM International Conference on Computer-Aided Design, pp 164-170, San Jose, CA, November 2002 download pdf

P. D’Alberto, A. Nicolau, A. Veidenbaum, and R. Gupta, “Static Analysis of Parameterized Loop Nests for Energy Efficient Use of Data Caches,” Second Workshop on Compilers and Operating Systems for Low Power (COLP’01), pp 11.1—11.7, Barcellona, Spain, September 2001

M. Mamidipaka, D. Hirschberg, and N. Dutt, “Low Power Address Encoding Using Self-Organizing Lists,” ISLPED-01, August 2001

J. Liu, P. Chou, N. Bagherzadeh, and F. Kurdahi, “Power-Aware Scheduling Under Timing Constraints for Mission-Critical Embedded Systems,” Proceedings of the 38th Design Automation Conference, pp 840-845, Las Vegas, NV, June 2001

S. Gupta, N. Savoiu, S. Kim, N. Dutt, R. Gupta, and A. Nicolau, “Speculation Techniques for High Level Synthesis of Control Intensive Designs,” Proceedings of the 38th Design Automation Conference, pp 269-272, Las Vegas, NV, June 2001

I. Bayraktaroglu and A. Orailoglu, “Test Volume and Application Time Reduction Through Scan Chain Concealment,” Proceedings of the 38th Design Automation Conference, pp 151-155, Las Vegas, NV, June 2001

P. Petrov and A. Orailoglu, “Speeding Up Control-Dominated Applications Through Microarchitectural Customizations in Embedded Processors,” Proceedings of the 38th Design Automation Conference, pp 512-517, Las Vegas, NV, June 2001

S. Almukhaizim, P. Petrov and A. Orailoglu, “Low-Cost, Software-Based Self-Test Methodologies for Performance Faults in Processor Control Subsystems,” Proceedings of the IEEE Custom Integrated Circuits Conference, San Diego, CA, May 2001

P. Grun, N. Dutt, and A. Nicolau, “Access Pattern Based Local Memory Customization for Low Power Embedded Systems,” Proceedings of the Design Automation and Test in Europe Conference (DATE 2001), Munich, Germany, March 2001