Conference Proceedings

S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt, and N. Venkatasubramanian, “Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices,” ESTIMedia 2003, First Workshop on Embedded Systems for Real-Time Multimedia, Newport Beach, CA, October 2003. download pdf

E. Gaudette, M. Moussa, and I. G. Harris, “A Method for the Evaluation of Behavioral Fault Models,” IEEE High-Level Design, Validation, and Test Workshop (HLDVT), November 2003. download pdf

S. Ghiasi, K. Nguyen, E Bozorgzadeh, and M Sarrafzadeh, “On Computation and Resource Management in Networked Embedded Systems,” International Conference on Parallel and Distributed Computing and Systems, pp 445-451, Marina del Rey, CA, November 3-5, 2003.  download pdf

F. Doucet, R. Gupta, and S. Shukla, “Introspection in System-Level Language Frameworks: Meta-Level or Integrated,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 382-387, Munich, Germany, March 2003 download pdf

A. Gerstlauer, H. Yu, and D. Gajski, “RTOS Modeling for System Level Design,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 130-135, Munich, Germany, March 2003 download pdf

A. Ghosh and T. Givargis, “Analytical Design Space Exploration of Caches for Embedded Systems,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 650-655, Munich, Germany, March 2003 download pdf

S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, “Dynamic Conditional Branch Balancing During the High-Level Synthesis of Control-Intensive Designs,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 270-275, Munich, Germany, March 2003 download pdf

M. Mamidipaka and N. Dutt, “On-Chip Stack Based Memory Organization for Low Power Embedded Architectures,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 1082-1087, Munich, Germany, March 2003 download pdf

D. Nicolaescu, A. Veidenbaum, and A. Nicolau, “Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 1064-1068, Munich, Germany, March 2003 download pdf

C. Pan, N. Bagherzadeh, A. Kamalizad, and A. Koohi, “Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 468-473, Munich, Germany, March 2003 download pdf

P. Petrov and A. Orailoglu, “Power Efficiency Through Application-Specific Instruction Memory Transformations,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 30-35, Munich, Germany, March 2003 download pdf

W. Roa and A. Orailoglu, “Virtual Compression Through Test Vector Switching for Scan Based Design,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 104-109, Munich, Germany, March 2003 download pdf

M. Sánchez-Élez, M. Férnandez, M. Anido, H. Du, N. Bagherzadeh, and R. Hermida, “Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures,” Design, Automation, and Test in Europe Conference (DATE ‘03), pp 36-41, Munich, Germany, March 2003
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Z. Zeng, Q. Zhang, I. G. Harris, and M. Ciesielski, “Fast Computation of Data Correlation Using BDDs,” IEEE/ACM Design Automation and Test in Europe Conference (DATE ’03), Munich, Germany, March 2003 download pdf

P. Mishra and N. Dutt, “A Methodology for Validation of Microprocessors using Equivalence Checking Communication Refinement for System Level Design,” 4th Workshop on Microprocessor Test and Verification, Austin, TX, May 2003

S. Abdi, D. Shin, and D. Gajski, “Automatic Communication Refinement for System Level Design,” 40th Design Automation Conference, pp 300-305, Anaheim, CA, June 2003 download pdf

E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh, “Optimal Integer Delay Budgeting on Directed Acyclic Graphs,” 40th Design Automation Conference, pp 300-305, Anaheim, CA, June 2003 download pdf

T. Givargis, “Improving Indexing for Cache Miss Reduction in Embedded Systems,” 40th Design Automation Conference, pp 875-880, Anaheim, CA, June 2003 download pdf

D. Li, Q. Xie, and P. Chou, “Scalable Modeling and Optimization of Mode Transitions Based on Decoupled Power Management Architecture,” 40th Design Automation Conference, pp 119-124, Anaheim, CA, June 2003 download pdf

R. Lysecky and F. Vahid, “On-Chip Logic Minimization,” 40th Design Automation Conference, pp 334-337, Anaheim, CA, June 2003 download pdf

W. Rao, I. Bayraktaroglu, and A. Orailoglu, “Test Application Time and Volume Compression Through Overlapping,” 40th Design Automation Conference, pp 732-737, Anaheim, CA, June 2003 download pdf

M. Reshadi, P. Mishra and N. Dutt, “Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation,” 40th Design Automation Conference, pp 758-763, Anaheim, CA, June 2003 download pdf

G. Stitt, R. Lysecky, and F. Vahid, “Dynamic Hardware/Software Partitioning: A First Approach,” 40th Design Automation Conference, pp 250-255, Anaheim, CA, June 2003 download pdf

P. Mishra, A. Kejariwal, and N. Dutt, “Rapid Exploration of Pipelined Processors Through Automatic Generation of Synthesizable RTL Models,” 14th IEEE Workshop on Rapid System Prototyping, pp 226-232, San Diego, CA, June 2003

P. Chou, C. Park, J. Park, K. Pham, and J. Liu, “B#: a Battery Emulator and Power Profiling Instrument,” 2003 International Symposium on Low Power Electronics and Design, pp 288-293, Seoul, Korea, August 2003 download pdf

P.Heydari and Y. Zhang, “A Novel High Frequency, High-Efficiency, Differential Class-E Power Amplifier in 0.18um CMOS, Payam Heydari, and Ying Zhang,” 2003 International Symposium on Low Power Electronics and Design, pp 455-458 Seoul, Korea, August 2003 download pdf

J. Lee, K. Choi, and N. Dutt, “Energy-Efficient Instruction Set Synthesis for Application-Specific Processors,” 2003 International Symposium on Low Power Electronics and Design, pp 330-333, Seoul, Korea, August 2003download pdf

D. Nicolaescu, A. Veidenbaum, and A. Nicolau, “Reducing Data Cache Energy Consumption via Cached Load/Store Queue,” 2003 International Symposium on Low Power Electronics and Design, pp 252-257, Seoul, Korea, August 2003 download pdf

D. A. Fernandes and I. G. Harris, “Application of Built in Self-Test for Interconnect Testing of FPGAs,” IEEE International Test Conference, September 2003 download pdf

A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, and A. Nicolau, “Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints,” Design, Automation and Test in Europe Conference, pp 168-175, Paris, France, March 2002 download pdf

I. Bayraktaroglu and A. Orailodlu, “Gate Level Fault Diagnosis in Scan-Based BIST,” Design, Automation and Test in Europe Conference, pp 376-381, Paris, France, March 2002 download pdf

E. Cota, L. Carro, A. Orailoglu, and M. Lubaszewski, “Test Planning and Design Space Exploration in a Core-Based Environment,” Design, Automation and Test in Europe Conference, pp 478-485, Paris, France, March 2002 download pdf

F. Doucet, S. Shukla, R. Gupta, and M. Otsuka, “An Environment for Dynamic Component Composition for Efficient Co-Design,” Design, Automation and Test in Europe Conference, pp 736-743, Paris, France, March 2002 download pdf

P. Grun, N. Dutt, and A. Nicolau, “Memory System Connectivity Exploration,” Design, Automation and Test in Europe Conference, pp 894-901, Paris, France, March 2002
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A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau, “An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Widths ISAs,” Design, Automation and Test in Europe Conference, pp 402-408, Paris, France, March 2002 download pdf

S. Irani, S. Shukla, and R. Gupta, “Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Saving States,” Design, Automation and Test in Europe Conference, pp 117-123, Paris, France, March 2002 download pdf

P. Mishra, H. Tomiyama, N. Dutt, and A. Nicolau, “Automatic Verification of In-Order Execution in Microprocessors with Fragmented Pipelines and Multicycle Functional Units,” Design, Automation and Test in Europe Conference, pp 36-43, Paris, France, March 2002 download pdf

P. Petrov and A. Orailoglu, “Power Efficient Embedded Processor IP’s Through Application-Specific Tag Compression in Data Caches,” Design, Automation and Test in Europe Conference, pp 1065-1071, Paris, France, March 2002 download pdf

S. Reda and A. Orailoglu, “Reducing Test Application Time Through Test Data Mutation Encoding,” Design, Automation and Test in Europe Conference, pp 387-393, Paris, France, March 2002 download pdf

M. Sánchez-Élez, M. Férnandez, R. Maestre, R. Hermida, N. Bagherzadeh, and F. Kurdahi, “A Complete Data Scheduler for Multi-Context Reconfigurable Architectures,” Design, Automation and Test in Europe Conference, pp 547-552, Paris, France, March 2002 download pdf

N. Savoiu, S. Shukla, and R. Gupta, “Automatic Concurrency Re-assignment in High Level System Models for Efficient System-Level Simulation,” Design, Automation and Test in Europe Conference, pp 875-881, Paris, France, March 2002 download pdf

W. Tang, R. Gupta, and A. Nicolau, “Power Savings in Embedded Processors Through Decode Filter Cache,” Design, Automation and Test in Europe Conference, pp 443-448, Paris, France, March 2002 download pdf