Conference Proceedings

S. Abdi, D. Shin, and D. Gajski, “Automatic Communication Refinement for System Level Design,” 40th Design Automation Conference, pp 300-305, Anaheim, CA, June 2003 download pdf

E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh, “Optimal Integer Delay Budgeting on Directed Acyclic Graphs,” 40th Design Automation Conference, pp 300-305, Anaheim, CA, June 2003 download pdf

T. Givargis, “Improving Indexing for Cache Miss Reduction in Embedded Systems,” 40th Design Automation Conference, pp 875-880, Anaheim, CA, June 2003 download pdf

D. Li, Q. Xie, and P. Chou, “Scalable Modeling and Optimization of Mode Transitions Based on Decoupled Power Management Architecture,” 40th Design Automation Conference, pp 119-124, Anaheim, CA, June 2003 download pdf

R. Lysecky and F. Vahid, “On-Chip Logic Minimization,” 40th Design Automation Conference, pp 334-337, Anaheim, CA, June 2003 download pdf

W. Rao, I. Bayraktaroglu, and A. Orailoglu, “Test Application Time and Volume Compression Through Overlapping,” 40th Design Automation Conference, pp 732-737, Anaheim, CA, June 2003 download pdf

M. Reshadi, P. Mishra and N. Dutt, “Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation,” 40th Design Automation Conference, pp 758-763, Anaheim, CA, June 2003 download pdf

G. Stitt, R. Lysecky, and F. Vahid, “Dynamic Hardware/Software Partitioning: A First Approach,” 40th Design Automation Conference, pp 250-255, Anaheim, CA, June 2003 download pdf

P. Mishra, A. Kejariwal, and N. Dutt, “Rapid Exploration of Pipelined Processors Through Automatic Generation of Synthesizable RTL Models,” 14th IEEE Workshop on Rapid System Prototyping, pp 226-232, San Diego, CA, June 2003

P. Chou, C. Park, J. Park, K. Pham, and J. Liu, “B#: a Battery Emulator and Power Profiling Instrument,” 2003 International Symposium on Low Power Electronics and Design, pp 288-293, Seoul, Korea, August 2003 download pdf

P.Heydari and Y. Zhang, “A Novel High Frequency, High-Efficiency, Differential Class-E Power Amplifier in 0.18um CMOS, Payam Heydari, and Ying Zhang,” 2003 International Symposium on Low Power Electronics and Design, pp 455-458 Seoul, Korea, August 2003 download pdf

J. Lee, K. Choi, and N. Dutt, “Energy-Efficient Instruction Set Synthesis for Application-Specific Processors,” 2003 International Symposium on Low Power Electronics and Design, pp 330-333, Seoul, Korea, August 2003download pdf

D. Nicolaescu, A. Veidenbaum, and A. Nicolau, “Reducing Data Cache Energy Consumption via Cached Load/Store Queue,” 2003 International Symposium on Low Power Electronics and Design, pp 252-257, Seoul, Korea, August 2003 download pdf

D. A. Fernandes and I. G. Harris, “Application of Built in Self-Test for Interconnect Testing of FPGAs,” IEEE International Test Conference, September 2003 download pdf

L. Cai and D. Gajski, “A Transaction Level Modeling: An Overview,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 19-24,Newport Beach, CA, October 2003
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S. Cotterell, F. Vahid, W. Najjar and H. Hsieh, “First Results with eBlocks: Embedded Systems Building Blocks,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 168-175 Newport Beach, CA, October 2003 download pdf

A. Koohi, N. Bagherzadeh, and C. Pan, “A Fast Parallel Reed-Solomon Decoder on a Reconfigurable Architecture,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 59-64,Newport Beach, CA, October 2003 download pdf

B. Mohebbi, E. Filho, R. Maestre, M. Davies, and F. Kurdahi, “A Case Study of Mapping a Software Defined Radio (SDR) Application on a Reconfigurable DSP Core,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 103-108, Newport Beach, CA, October 2003 download pdf

M. Reshadi, N. Bansa, P. Mishra and N. Dutt, “An Efficient Retargetable Framework for Instruction-Set Simulation,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 13-18, Newport Beach, CA, October 2003 download pdf

H. Yu, A. Gerstlauer, and D. Gajski, “RTOS Scheduling in Transaction Level Models,” First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp 31-36, Newport Beach, CA,October 2003 download pdf

S. Pasricha, and A. Veidenbaum, “Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches,” International Conference on Computer Design (ICCD 2003), San Jose, CA, October 2003 download pdf

S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt, and N. Venkatasubramanian, “Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices,” ESTIMedia 2003, First Workshop on Embedded Systems for Real-Time Multimedia, Newport Beach, CA, October 2003. download pdf

E. Gaudette, M. Moussa, and I. G. Harris, “A Method for the Evaluation of Behavioral Fault Models,” IEEE High-Level Design, Validation, and Test Workshop (HLDVT), November 2003. download pdf

S. Ghiasi, K. Nguyen, E Bozorgzadeh, and M Sarrafzadeh, “On Computation and Resource Management in Networked Embedded Systems,” International Conference on Parallel and Distributed Computing and Systems, pp 445-451, Marina del Rey, CA, November 3-5, 2003.  download pdf

S. Cotterell and F. Vahid, “Tuning of Loop Cache Architectures to Programs in Embedded System Designs,” International Symposium on System Synthesis, pp 8-13, Kyoto, Japan, October 2002 download pdf

A. Gerstlauer and D. Gajski, “System-Level Abstraction Semantics,” International Symposium on System Synthesis, pp 231-236, Kyoto, Japan, October 2002 download pdf

S. Gupta, M. Reshadi, N. Saviou, N. Dutt, and A. Nicolau, “Dynamic Common Sub-Expression Elimination During Scheduling in High-Level Synthesis,” International Symposium on System Synthesis, pp 261-266, Kyoto, Japan, October 2002 download pdf

J. Liu, P. H. Chou, and N. Bagherzadeh, “Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors,” International Symposium on System Synthesis, pp 14-19, Kyoto, Japan, October 2002 download pdf

M. Mamidipaka, N. Dutt, and D. Hirschberg, “Efficient Power Reduction Techniques for Time Multiplexed Address Buses,” International Symposium on System Synthesis, pp 207-212, Kyoto, Japan, October 2002 download pdf

W. Mueller, R. Doemer, and A. Gerstlauer, “The Formal Execution Semantics of SpecC,” International Symposium on System Synthesis, pp 150-155, Kyoto, Japan, October 2002 download pdf

J. Peng and D. Gajski, “Optimal Message Passing for Data Coherency in Distributed Architecture,” International Symposium on System Synthesis, pp 20-25, Kyoto, Japan, October 2002 download pdf

P. Petrov and A. Orailoglu, “Low-Power Data Memory Communication for Application-Specific Embedded Processors,” International Symposium on System Synthesis, pp 219-224, Kyoto, Japan, October 2002 download pdf

N. Saviou, S. K. Shukla, and R. Gupta, “Efficient Simulation of Synthesis-Oriented System Level Designs,” International Symposium on System Synthesis, pp 168-173, Kyoto, Japan, October 2002 download pdf