Location: Paris, France
Web Site: http://www.date-conference.com/
J. Aragon, D. Nicolaescu, A. Veidenbaum, and A. Badulescu, “Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1374-1375, February 16-20, 2004
B. Arslan and A. Orailoglu, “Circular-Scan: A Scan Architecture for Test Cost Reduction,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1290-1295, February 16-20, 2004
N. Bansal, S. Gupta, N. Dutt, A. Nicolau, and R. Gupta, “Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 474-479, February 16-20, 2004
A. Gordon-Ross, F. Vahid, and N. Dutt, “Automatic Tuning of Two-Level Caches to Embedded Applications,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 208-213, February 16-20, 2004
S. Gupta, N. Dutt, A. Nicolau, and R. Gupta, “Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 114-120, February 16-20, 2004
M. Heath, W. Burleson, and I. G. Harris, “Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC,” IEEE/ACM Design Automation and Test in Europe Conference (DATE ’04), Paris, France, February 16-20, 2004 download pdf
R. Lysecky, and F. Vahid, “A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 480-485, February 16-20, 2004
P. Mishra, N. Dutt, “Graph-Based Functional Test Program Generation for Pipelined Processors,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 182-187, February 16-20, 2004
A. Nacul and T. Givargas, “Dynamic Voltage and Cache Reconfiguration for Low Power,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 1376-1378, February 16-20, 2004
O. Sinanoglu and A. Orailoglu, “Scan Power Minimization Through Stimulus and Response Transformations,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 404-409, February 16-20, 2004
C. Zhang and F. Vahid, “Using a Victim Buffer in an Application-Specific Memory Hierarchy,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 220-227, February 16-20, 2004
C. Zhang, F. Vahid, and R. Lysecky, “A Self-Tuning Cache Architecture for Embedded Systems,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 142-147, February 16-20, 2004
C. Zhang, J. Yang, and F. Vahid, “Low Static-Power Frequent-Value Data Caches,” Design, Automation and Test in Europe Conference (DATE ‘04), Paris, France, pp 214-219, February 16-20, 2004