DAC'98 Table of Contents

Cover Page
General Chair's Welcome
Executive Committee
Technical Program Committee
1998 Best Paper Award
ACSEE Undergraduate Scholarships
Design Automation Conference Graduate Scholarship Awards
1998 IEEE Fellows
SIGDA Meritorious Service Award
36th Call for Papers
Reviewers
Opening Keynote Address - William J. Spencer
Thursday Keynote Address - George H.Heilmeier

Executive Plenary Panel: Customers, Vendors, and Universities: Determining the Future of EDA Together

Session 1: Interfaces for Design Reuse

1.1 Embedded Tutorial: Asynchronous Interface Specification, Analysis and Synthesis

Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev [p. 2]

1.2 Automatic Synthesis of Interfaces between Incompatible Protocols

Roberto Passerone, James A. Rowson, Alberto Sangiovanni-Vincentelli [p. 8]

1.3 Automated Composition of Hardware Components

James Smith, Giovanni De Micheli [p. 14]

Session 2: Analog and Mixed-Signal Design Tools

2.1 Multilevel Integral Equation Methods for the Extraction of Substrate Coupling Parameters in Mixed-Signal IC's

Mike Chou, Jacob White [p. 20]

2.2 Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterisation

Alper Demir, Amit Mehrotra, Jaijeet Roychowdhury [p. 26]

2.3 Efficient Analog Test Methodology Based on Adaptive Algorithms

Luigi Carro, Marcelo Negreiros [p. 32]

2.4 General AC Constraint Transformation for Analog ICs

B. G. Arsintescu, E. Charbon, E. Malavasi, U. Choudhury, W. H. Kao [p. 38]

Session 3: University Design Contest

3.1 Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver

Jacob Rael, Ahmadreza Rofougaran, Asad Abidi [p. 44]

3.2 A Video Signal Processor for MIMD Multiprocessing

Jörg Hilgenstock, Klaus Herrmann, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch [p. 50]

3.3 Realization of a Programmable Parallel DSP for High Performance Image Processing Applications

Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch [p. 56]

3.4 A Multiprocessor DSP System Using PADDI-2

Roy A. Sutton, Vason P. Srini, Jan M. Rabaey [p. 62]

3.5 Design and Implementation of the NUMAchine Multiprocessor

A. Grbic, S. Brown, S. Caranci, R. Grindley, M.Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic, Z. Zilic [p. 66]

Session 4: Embedded System Design and Exploration

4.1 Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement

James Shin Young, Josh MacDonald, Michael Shilman, Abdallah Tabbara, Paul Hilfinger, A. Richard Newton [p. 70]

4.2 Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer

Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man [p. 76]

4.3 Design Space Exploration Algorithm for Heterogeneous Multi-processor Embedded System Design

Ireneusz Karkowski, Henk Corporaal [p. 82]

4.4 Modal Processes: Towards Enhanced Retargetability through Control Composition of Distributed Embedded Systems

Pai Chou, Gaetano Borriello [p. 88]

Session 5: Taming Noise in Deep-Submicron Digital ICs

5.1 Embedded Tutorial: Design Methodologies for Noise in Digital Integrated Circuits

Kenneth L. Shepard [p. 94]

Panel: Taming Noise in Deep Submicron Digital Integrated Circuits

Chair: Nagaraj NS
Organizers: Kenneth Shepard, Takahide Inoue
Panel Members: Chris Houghton, Barbara Chappell, Xiaonan Zhang, John MacDonald, John McBride, Bob Masleid [p. 100]

Session 6: Control and Data Driven High Level Synthesis

6.1 FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-flow Intensive Behavioral Descriptions

Ganesh Lakshminarayana, Niraj K. Jha [p. 102]

6.2 Incorporating Speculative Execution into Scheduling of Control-flow Intensive Behavioral Descriptions

Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha [p. 108]

6.3 The DT-Model: High-Level Synthesis Using Data Transfers

Shantanu Tarafdar, Miriam Leeser [p. 114]

6.4 Rate Optimal VLSI Design from Data Flow Graph

Moonwook Oh, Soonhoi Ha [p. 118]

Session 7: Synthesis Flow in Deep Submicron Technologies

7.1 Embedded Tutorial: Planning for Performance

Ralph H. J. M. Otten, Robert K. Brayton [p. 122]

7.2 A DSM Design Flow: Putting Floorplanning, Technology-Mapping, and Gate-Placement Together

Amir H. Salek, Jinan Lou, Massoud Pedram [p. 128]

Session 8: Environment for Collaborative Design

8.1 Framework Encapsulations: A New Approach to CAD Tool Interoperability

Peter R. Sutton, Stephen W. Director [p. 134]

8.2 A Geographically Distributed Framework for Embedded System Design and Validation

Ken Hines, Gaetano Borriello [p. 140]

8.3 WELD - An Environment for Web-Based Electronic Design

Francis L. Chan, Mark D. Spiller, A. Richard Newton [p. 146]

Session 9: New Methods in Functional Verification

9.1 OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification

Farzan Fallah, Srinivas Devadas, Kurt Keutzer [p. 152]

9.2 User Defined Coverage - A Tool Supported Methodology for Design Verification

Raanan Grinwald, Eran Harel, Michael Orgad, Shmuel Ur, Avi Ziv [p. 158]

9.3 Enhanced Visibility and Performance in Functional Verification by Reconstruction

Joshua Marantz [p. 164]

9.4 Virtual Chip: Making Functional Models Work on Real Target Systems

Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung [p. 170]

Session 10: Panel: Hardware/Software Co-Design: The Next Embedded System Design Challenge

Session 11: System-Level Power Optimization

11.1 Power Optimization of Variable Voltage Core-Based Systems

Inki Hong, Darko Kirovski, Gang Qu, Miodrag M. Potkonjak, Mani B. Srivastava [p. 176]

11.2 Policy Optimization for Dynamic Power Management

G. A. Paleologo, L. Benini, A. Bogliolo, G. De Micheli [p. 182]

11.3 A Framework for Estimating and Minimizing Energy Dissipation of Embedded HW/SW Systems

Yanbing Li, Jörg Henkel [p. 188]

Session 12: Boolean Methods

12.1 Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain:A Case Study with Boolean Satisfiability

Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi [p. 194]

12.2 Fast Exact Minimization of BDDs

Rolf Drechsler, Nicole Drechsler, Wolfgang Günther [p. 200]

12.3 Boolean Matching for Large Libraries

Uwe Hinsberger, Reiner Kolla [p. 206]

Session 13: Extraction and Modeling for Interconnect

13.1 A Fast Hierarchical Algorithm for 3-D Capacitance Extraction

Weiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu [p. 212]

13.2 Boundary Element Method Macromodels for 2-D Hierarchical Capacitance Extraction

E. Aykut Dengi, Ronald A. Rohrer [p. 218]

13.3 Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered Green's Functions

Jinsong Zhao, Wayne W. M. Dai, Sharad Kapur, David E. Long [p. 224]

Session 14: Processor Design and Simulation

14.1 Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor

Nevine Nassif, Madhav P. Desai, Dale H. Hall [p. 230]

14.2 A Top-down Design Environment for Developing Pipelined Datapaths

Robert McGraw, James H. Aylor, Robert H. Klenke [p. 236]

14.3 Validation of an Architectural Level Power Analysis Technique

Rita Yu Chen, Robert M. Owens, Mary Jane Irwin, Raminder S. Bajwa [p. 242]

14.4 Design Methodology of a 200MHz Superscalar Microprocessor: SH-4

Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura [p. 246]

Session 15: Panel: How Much Analog Does a Designer Need To Know for Successful Mixed-Signal Design?

Session 16: Performance Modeling and Characterization for Embedded Systems

16.1 Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance

G. de Veciana, M. Jacome, J.-H. Guo [p. 251]

16.2 A Tool for Performance Estimation of Networked Embedded End-Systems

Asawaree Kalavade, Pratyush Moghé [p. 257]

16.3 Rate Derivation and Its Applications to Reactive, Real-time Embedded Systems

Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta [p. 263]

Session 17: Advances in Placement and Partitioning

17.1 Generic Global Placement and Floorplanning

Hans Eisenmann, Frank M. Johannes [p. 269]

17.2 Congestion Driven Quadratic Placement

Phiroze N. Parakh, Richard B. Brown, Karem A. Sakallah [p. 275]

17.3 Potential_NRG: Placement with Incomplete Data

Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh [p. 279]

17.4 Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication

Wen-Jong Fang, Allen C.-H. Wu [p. 283]

17.5 Multi-pad Power/Ground Network Design for Uniform Distribution of Ground Bounce

Jaewon Oh, Massoud Pedram [p. 287]

Session 18: Parasitic Device Extraction and Interconnect Modeling

18.1 Layout Extraction and Verification Methodology for CMOS I/O Circuits

Tong Li, Sung-Mo (Steve) Kang [p. 291]

18.2 A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects

Nuno Marques, Mattan Kamon, Jacob White, L. Miguel Silveira [p. 297]

18.3 Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis

Byron Krauter, Sharad Mehrotra [p. 303]

Session 19: Design Optimization for DSP

19.1 A Methodology for Guided Behavioral-Level Optimization

Lisa Guerra, Miodrag Potkonjak, Jan Rabaey [p. 309]

19.2 A Programming Environment for the Design of Complex High Speed ASICs

Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens [p. 315]

19.3 Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor

Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith [p. 321]

Session 20: Panel: User Experience with High Level Formal Verification

Chair: Gerry Musgrave
Organizers: Randal E. Bryant, Gerry Musgrave
Panel Members: Fumiyasu Hirose, Michael Payer, Pierre Aulagnier, Allan Silbert, John Van Tassel [p. 327]

Session 21: Bridging the Gap Between Simulation and Formal Verification

21.1 Embedded Tutorial: What's Between Simulation and Formal Verification?

David L. Dill [p. 328]

Session 22: Logic Optimization

22.1 Optimal FPGA Mapping and Retiming with Efficient Initial State Computation

Jason Cong, Chang Wu [p. 330]

22.2 M32: A Constructive Multilevel Logic Synthesis System

Victor N. Kravets, Karem A. Sakallah [p. 336]

22.3 Efficient Boolean Division and Substitution

Shih-Chieh Chang, David Ihsin Cheng [p. 342]

22.4 Delay-Optimal Technology Mapping by DAG Covering

Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar [p. 348]

22.5 A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries

David S. Kung [p. 352]

Session 23: Routing for Performance and Crosstalk

23.1 Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs

Jason Cong, Patrick H. Madden [p. 356]

23.2 Buffer Insertion for Noise and Delay Optimization

Charles J. Alpert, Anirudh Devgan, Stephen T. Quay [p. 362]

23.3 Table-Lookup Methods for Improved Performance-Driven Routing

John Lillis, Premal Buch [p. 368]

23.4 Global Routing with Crosstalk Constraints

Hai Zhou, D.F. Wong [p. 374]

23.5 Timing and Crosstalk Driven Area Routing

Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen [p. 378]

Session 24: Practical Optimization Methodologies for High Performance Design

24.1 Process Multi-Circuit Optimization

Arun Lokanathan, Jay Brockman [p. 382]

24.2 Migration:A New Technique to Improve Synthesized Designs through Incremental Customization

Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw [p. 388]

24.3 A Practical Repeater Insertion Method in High Speed VLSI Circuits

Julian Culetu, Chaim Amir, John MacDonald [p. 392]

24.4 Practical Experiences with Standard-Cell Based Datapath Design Tools - Do We Really Need Regular Layouts?

Paolo Ienne, Alexander Griebing [p. 396]

24.5 A Statistical Performance Simulation Methodology for VLSI Circuits

Michael Orshansky, James C. Chen, Chenming Hu [p. 402]

Session 25: RF IC Design Methodology

25.1 Embedded Tutorial: RF IC Design Challenges

Behzad Razavi [p. 408]

25.2 Tools and Methodology for RF IC Design

Al Dunlop, Alper Demir, Peter Feldmann, Sharad Kapur, David Long, Robert Melville, Jaijeet Roychowdhury [p. 414]

25.3 Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printing Circuit Boards

Frank Y. Yuan [p. 421]

Session 26: Theory and Practice in High Level Synthesis

26.1 Efficient Coloring of a Large Spectrum of Graphs

Darko Kirovski, Miodrag Potkonjak [p. 427]

26.2 Arithmetic Optimization Using Carry-Save-Adders

Taewhan Kim, William Jao, Steve Tjiang [p. 433]

26.3 Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions

Ganesh Lakshminarayana, Niraj K. Jha [p. 439]

Session 27: BDD Approximation Techniques

27.1 Approximation and Decomposition of Binary Decision Diagrams

Kavita Ravi, Kenneth L. McMillan, Thomas R. Shiple, Fabio Somenzi [p. 445]

27.2 Approximate Reachability with BDDs Using Overlapping Projections

Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark A. Horowitz [p. 451]

27.3 Incremental CTL Model Checking Using BDD Subsetting

Abelardo Pardo, Gary D. Hachtel [p. 457]

Session 28: Interconnect Modeling and Timing Simulation

28.1 PRIMO: Probability Interpretation of Moments for Delay Calculation

Rony Kay, Lawrence Pileggi [p. 463]

28.2 ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models

Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas [p. 469]

28.3 Extending Moment Computation to 2-Port Circuit Representations

Fang-Jou Liu, Chung-Kuan Cheng [p. 473]

28.4 Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation

Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov [p. 477]

Session 29: Low Power Design Using Multiple Thresholds and Supplies

29.1 Design Methodology of Ultra Low-power MPEG4 Codec Core Exploiting Voltage Scaling Techniques

Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda [p. 483]

29.2 Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits

Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De [p. 489]

29.3 MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns

James Kao, Siva Narendra, Anantha Chandrakasan [p. 495]

Session 30: Panel: Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective

Session 31: Software Synthesis and Retargetable Compilation

31.1 Software Synthesis of Process-Based Concurrent Programs

Bill Lin [p. 502]

31.2 Don't Care-Based BDD Minimization for Embedded Software

Youpyo Hong, Peter A. Beerel, Luciano Lavagno, Ellen M. Sentovich [p. 506]

31.3 Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator

Silvina Hanono, Srinivas Devadas [p. 510]

31.4 Code Compression for Embedded Systems

Haris Lekatsas, Wayne Wolf [p. 516]

Session 32: Formal Methods in Functional Verification

32.1 A Decision Procedure for Bit-Vector Arithmetic

Clark W. Barrett, David L. Dill, Jeremy R. Levitt [p. 522]

32.2 Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability

Farzan Fallah, Srinivas Devadas, Kurt Keutzer [p. 528]

32.3 Automatic Generation of Assertions for Formal Verification of PowerPC ^TM Microprocessor Arrays Using Symbolic Trajectory Evaluation

Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy [p. 534]

32.4 Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment

Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger [p. 538]

Session 33: Core Test and BIST

33.1 A Fast and Low Cost Testing Technique for Core-based System-on-Chip

Indradeep Ghosh, Sujit Dey, Niraj K. Jha [p. 542]

33.2 Introducing Redundant Computations in a Behavior for Reducing BIST Resources

Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer [p. 548]

33.3 A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis

Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik [p. 554]

Session 34: Interconnect Analysis and Reliability in Deep Sub-Micron

34.1 Figures of Merit to Characterize the Importance of On-Chip Inductance

Yehea I. Ismail, Eby G. Friedman, Jose L. Neves [p. 560]

34.2 Layout Techniques for Minimizing On-Chip Interconnect Self Inductance

Yehia Massoud, Steve Majors, Tareq Bustami, Jacob White [p. 566]

34.3 A Practical Approach to Static Signal Electromigration Analysis

Nagaraj NS, Frank Cano, Haldun Haznedar, Duane Young [p. 572]

Session 35: Panel: Design Productivity: How to Measure It, How to Improve It

Session 36: Timing Analysis

36.1 Hierarchical Functional Timing Analysis

Yuji Kukimoto, Robert K. Brayton [p. 580]

36.2 Making Complex Timing Relationships Readable: Presburger Formula Simplification Using Don't Cares

Tod Amon, Gaetano Borriello, Jiwen Liu [p. 586]

36.3 Delay Estimation of VLSI Circuits from a High-Level View

Mahadevamurty Nemani, Farid N. Najm [p. 591]

36.4 TETA: Transistor-Level Engine for Timing Analysis

Florentin Dartu, Lawrence T. Pileggi [p. 595]

Session 37: New Techniques in State Space Explorations

37.1 Validation with Guided Search of the State Space

C. Han Yang, David L. Dill [p. 599]

37.2 Efficient State Classification of Finite State Markov Chains

Aiguo Xie, Peter A. Beerel [p. 605]

37.3 An Implicit Algorithm for Finding Steady States and its Application to FSM Verification

Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee [p. 611]

37.4 Hybrid Verification Using Saturated Simulation

Adnan Aziz, Jim Kukula, Tom Shiple [p. 615]

Session 38: Advanced ATPG Techniques

38.1 Fast State Verification

Dechang Sun, Bapiraju Vinnakota, Wanli Jiang [p. 619]

38.2 A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance

Aiman El-Maleh, Mark Kassab, Janusz Rajski [p. 625]

38.3 Fault-Simulation Based Design Error Diagnosis for Sequential Circuits

Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu [p. 632]

Session 39: Practical Experience of Functional Verification for Complex ICs

39.1 Functional Verification of a Multiple-Issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor

Scott Taylor, Michael Quinn, Darren Brown, Nathan Dohm, Scot Hildebrandt, James Huggins, Carl Ramey [p. 638]

39.2 Design Reliability - Estimation Through Statistical Analysis of Bug Discovery Data

Yossi Malka, Avi Ziv [p. 644]

39.3 Functional Verification of Large ASICs

Adrian Evans, Allan Silburt, Gary Vrckovnik, Thane Brown, Mario Dufresne, Geoffrey Hall, Tung Ho, Ying Liu [p. 650]

Session 40: Panel: The EDA Start-up Experience: The First Product

Session 41: Fast Functional Simulation

41.1 Embedded Tutorial: Digital System Simulation: Methodologies and Examples

Kunle Olukotun, Mark Heinrich and David Ofelt [p. 658]

41.2 Hybrid Techniques for Fast Functional Simulation

Yufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz []p. 664]

41.3 A Reconfigurable Logic Machine for Fast Event-Driven Simulation

Jerry Bauer, Michael Bershteyn, Ian Kaplan, Paul Vyedin [p. 668]

Session 42: Power Estimation and Modeling

42.1 Parallel Algorithms for Power Estimation

Victor Kim, Prithviraj Banerjee [p. 672]

42.2 A Power Macromodeling Technique Based on Power Sensitivity

Zhanping Chen, Kaushik Roy [p. 678]

42.3 Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics

Qinru Qiu, Qing Wu, Massoud Pedram [p. 684]

42.4 An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits

Byunggyu Kwak, Eun Sei Park [p. 690]

42.5 Using Complementation and Resequencing to Minimize Transitions

Rajeev Murgai, Masahiro Fujita, Arlindo Oliveira [p. 694]

Session 43: Technology Mapping for Programmable Logic

43.1 Technology Mapping for Large Complex PLDs

Jason Helge Anderson, Stephen Dean Brown [p. 698]

43.2 Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs

Jason Cong, Songjie Xu [p. 704]

43.3 Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs

Madhukar R. Korupolu, K. K. Lee, D. F. Wong [p. 708]

43.4 Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis

Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang [p. 712]

43.5 In-Place Power Optimization for LUT-Based FPGAs

Balakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi [p. 718]

43.6 A Re-engineering Approach to Low Power FPGA Design Using SPFD

Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang [p. 722]

Session 44: Power Dissipation and Distribution in High Performance Processors

44.1 Power Considerations in the Design of the Alpha 21264 Microprocessor

Michael K. Gowan, Larry L. Biro, Daniel B. Jackson [p. 726]

44.2 Reducing Power in High-Performance Microprocessors

Vivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav Mehta, Rakesh Patel, Franklin Baez [p. 732]

44.3 Design and Analysis of Power Distribution Networks in PowerPC ^TM- Microprocessors

Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden [p. 738]

44.4 Full-Chip Verification Methods for DSM Power Distribution Systems

Gregory Steele, David Overhauser, Steffen Rochel, Syed Zakir Hussain [p. 744]

Session 45: Challenge in the Test on System-On-A-Chip Era

Panel: System Chip Test Challenges, Are There Solutions Today?

45.1 Embedded Tutorial: System-Chip Test Strategies