• NISC: No-Instruction-Set-Computer

    Release Date: May 2008 (NISC Toolset 2008.05)NISC Demo: https://www.cecs.uci.edu/~nisc/  No-Instruction-Set-Computer (NISC) Technology is the next generation of tools for Design Synthesis. With NISC Technology, you can simultaneously gain higher productivity and better quality of results. Other techniques only offer one of these benefits. Two popular approaches for designing digital systems: Low-level design at Register Transfer Level (RTL). […]

  • Hardware-Accelerated Formal Verification

    by Prof. Masahiro FujitaVLSI Design and Education Center University of Tokyo, Tokyo, Japan McDonnell Douglas Auditorium, University of California, Irvine Distinguished Lecture, April 29, 2008 Abstract

  • ESE: Embedded System Environment

    Release Date: March 28, 2008Web Site: https://www.cecs.uci.edu/~ese/ ESE is a toolset for modeling, synthesis and validation of multi-processor embedded system designs. It builds on over 15 years of research in system level design at CECS under Prof. Daniel Gajski. It consists of two parts: ESE Front End and ESE Back End. ESE Front End provides automatic generation of SystemC transaction […]

  • CECS Faculty-Students Gathering 2007

    Faculty and students mingle at the 2007 CECS Student-Faculty Gathering, held in our new office at 2010 Anteater Instruction Research Building (AIRB).

  • Gabor Madl wins prestigious ACM Award

    Gabor Madl, a CECS graduate student pursuing a PhD in Computer Science, received the 2008 ACM SIGBED/SIGSOFT Frank Anger Memorial Award at the 2007 Embedded Systems Week Conference held in Salzburg, Austria. This award recognizes one student researcher from each of the professional societies (ACM SIGBED and ACM SIGSOFT), promoting the crossover of ideas between […]