Release Date: March 28, 2008
Web Site: https://www.cecs.uci.edu/~ese/
ESE is a toolset for modeling, synthesis and validation of multi-processor embedded system designs. It builds on over 15 years of research in system level design at CECS under Prof. Daniel Gajski. It consists of two parts: ESE Front End and ESE Back End.
ESE Front End provides automatic generation of SystemC transaction level models (TLMs) from graphical capture of system platform and application C/C++ code. ESE generated TLMs can be used either as virtual platforms for SW development or for fast and early timing estimation of system performance. The retargetable performance estimation utilizes the LLVM infrastructure.
ESE Back End provides automatic synthesis from TLM to Pin-Cycle Accurate Model (PCAM) consisting of RTL interfaces, system SW and prototype ready FPGA project files. ESE generated RTL can be synthesized using standard logic synthesis tools and system SW can be compiled along with application code for a given processor. ESE automatically creates Xilinx EDK projects for download to Xilinx boards.
The key advantages of ESE are huge productivity gain (provided by model automation and higher design abstraction) and ease of use for non-experts (provided by C-based and graphical design input). To learn more about ESE or to download ESE Front End, please visit the ESE Web Site.
D. Gajski, A. Gerstlauer, and S. Abdi, “Embedded System Design: Concepts and Tools,” ASP-DAC 2007 Pacifico Yokohama, Yokohama, Japan, January 23, 2007.