Contact Information
Heterogeneous Integration, Neuromorphic Hardware, Design and Optimization Methodologies
boris.vaisband@uci.edu
(949) 824-5991
https://borisvaisband.wixsite.com/think-team/contact-us
Professor Vaisband’s Research
Boris Vaisband is an Assistant Professor at the University of California, Irvine, working on heterogeneous systems integration. In 2024, he was the Acting Director of UCLA CHIPS, and from 2019 to 2024, an Assistant Professor at McGill University. He received a B.S. degree in Computer Engineering from the Technion- Israel Institute of Technology in 2011, and M.S. and Ph.D. degrees in Electrical Engineering from the University of Rochester, NY, in, respectively, 2012 and 2017. From 2017 to 2019, Prof. Vaisband was a Postdoctoral Scholar at UCLA. From 2008 to 2015, he held various hardware design positions at Intel, Cisco, and Google. Professor Vaisband is a senior member of the IEEE (’12), and a member of the IEEE Circuits and Systems Society (’16) and the IEEE Electronics Packaging Society (’18). His current research interests are in heterogeneous integration, advanced packaging, and neuromorphic systems, with a focus on circuits, EDA tools, and design methodologies for power delivery, communication, thermal aware design and floorplanning, and testing. Some applications of interest are ultra-large-scale artificial intelligence systems and high performance computing.
Research Interests
- Chiplet-Based Heterogeneous Integration: Communicating signals among multiple vertically stacked chiplets or across an entire wafer is a complex task. In some cases simple node-to-node signaling is possible, in other cases, a network architecture supporting fast, low area, and low energy communication protocols is required. Furthermore, challenges related to power delivery, thermal dissipation, test, hardware security, and synchronization, must also be addressed at scale.
- EDA for Chiplet-Based Systems: Designing chiplet-based systems is a novel challenge. A new abstraction layer must be defined that takes into account the heterogeneity of the chiplets, characteristics of the substrate, as well as addresses the large scale of such systems. Dedicated optimization algorithms and ML-based predictive models are required to enable the fast and efficient design of chiplet-based systems.
- Neuromorphic Hardware: Using charge-trap transistors (CTTs), which are fabricated in standard CMOS process, we obtain compute-in-memory devices that are able to store synaptic weights and perform a multiplication operation with incoming signals. These analog devices serve as synaptic array to analog and digital neuron designs enabling scalable low-power neural networks. We aim to build ultra-large scale neural networks useful for both ML tasks as well as brain emulation.