by Sudeep Pasricha (advisor: Prof. Nikil Dutt)
Date: May 12, 2008
With the increasing performance demands of emerging convergence applications and advances in process technology, Multiprocessor Systems-on-Chip (MPSoCs) are becoming prevalent in modern embedded systems. The on-chip communication architecture that interconnects the various components in such systems has a large and critical impact on the overall system performance, power, cost and reliability. Consequently, the design, exploration and implementation of on-chip communication architectures have become some of the most time-consuming activities for system designers in a typical MPSoC design flow. The task of on-chip communication architecture design is further hampered by a lack of state-of-the-art system-level tools and methodologies to cope with their increasingly significant role in systems today.
In this dissertation, we propose the COMMSYN framework for automated exploration and synthesis of on-chip communication architectures in emerging heterogeneous MPSoC applications. We have developed fast and accurate simulation and power estimation models for reliable on-chip communication architecture exploration early in the design flow. These models are used in our framework to make informed decisions during synthesis. COMMSYN enables a physical-implementation-aware and memory-architecture-aware on-chip communication architecture synthesis, comprehensively and automatically generating both the topology and protocol parameters, while trading off multiple design constraints such as power, performance, area and cost.Such a multi-faceted synthesis framework accrues many benefits for MPSoC designs such as improved design reliability and quality, better complexity management, reduced system cost and a faster time-to-market. The experiments on several industrial strength applications demonstrate the utility of the automated and comprehensive synthesis framework for MPSoC designs.