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NISC: No-Instruction-Set-Computer

May 10, 2008 @ 3:00 pm - 4:00 pm PDT

Release Date: May 2008 (NISC Toolset 2008.05)NISC Demo: https://www.cecs.uci.edu/~nisc/ 

No-Instruction-Set-Computer (NISC) Technology is the next generation of tools for Design Synthesis.
With NISC Technology, you can simultaneously gain higher productivity and better quality of results. Other techniques only offer one of these benefits.

Two popular approaches for designing digital systems:

  • Low-level design at Register Transfer Level (RTL).
    • Can lead to efficient IPs but the development time and cost is very high.
    • High-Level-Synthesis (HLS) goal: improve productivity
      • Automatically converts high-level description of the IP (e.g. written in C language) to RTL
      • Designer has little control over the quality of the generated RTL in terms of clock frequency, area, manufacturability, power, etc
        • Result quality typically bad.
  • High-level design using general-purpose or custom processors.
    • Development time and cost is much lower, but the efficiency and implementation quality is also much lower.
    • Application-Specific-Instruction-Processors (ASIP) goal: improve quality
      • Adds application-specific instructions to the processor
        • Finding suitable custom instructions and adding them to the toolset (compiler, simulator, etc.) is a very challenging task.
        • Because of their instruction-set, processors (including ASIPs) impose a minimum overhead in terms of area, power, and performance.
      • The processor-based implementation may become more appealing only when the IP design complexity is above a certain level (relatively very high).
        • Not suitable if you want to run a few algorithms or design a hardware block

D. Gajski, “NISC: The Ultimate Reconfigurable Component,” TR 03-28, October 1, 2003.
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May 10, 2008
3:00 pm - 4:00 pm PDT
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