Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
Dr. Hiroshi Nakamura, University of Tokyo, JapanOctober 19, 2009
12 events found.
Events
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Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA
Prof. Lei He, Electrical Engineering Department, UCLAOctober 9. 2009
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Algorithmic Code Optimization Using Conditional Expression Evaluation
by Mohammad Ali Ghodrat, University of California, IrvineSeptember 1, 2009
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Portable Direct Methanol Fuel Cell System for Green Computing
by Dr. Naehyuck ChangSeoul National University
CalIT2 Room 3008
Seminar, August 5, 2009 -
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Application Specific Multicore Chips for Medical Services
Dr. Iyad Al Khatib, Solidux Telecom ABStockholm, Sweden Engineering III 2430 July 24, 2009 Abstract
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Compiler-enabled Power-efficient Register File Protection
by Dr. Jongeun LeeEECS, Ulsan National Institute of Science and Technology,Korea
Donald Bren Hall (DBH) 3011 Date & Time
Seminar, July 22, 2009 -
Transducer Synthesis for Heterogeneous Multi-processor Systems
by Hansu Cho, University of California, IrvineJuly 9, 2009
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Automatic Generation and Verification of Transaction Level Models
by Lochi Yu, University of California, IrvineJune 18, 2009
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TransMutations: A framework for dynamic customization of retargetable compilers for embedded processors
by Ashok Halambi, University of California, IrvineJune 3, 2009
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Temperature Aware VLSI Design for Reduced Power and Reliability Enhancement
by Aseem Gupta, University of California, IrvineMay 29, 2009
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Model-based Analysis of Event-driven Distributed Real-time Embedded Systems
by Gabor Madl, University of California, IrvineMay 27, 2009
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Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design
Dr. Hiroshi Nakamura, University of Tokyo, JapanMay 4, 2009 (Lecture Cancelled)