by Ashok Halambi
Location: DBH 4013
Date and Time: June 3, 2009 2:00pm
Chancellor’s Professor Nikil Dutt (Chair)
Professor Alex Nicolau
Professor Alex Viedenbaum
Embedded systems continue to increase in functionality, complexity and connectivity. Programmable platforms, consisting of processors programmable in software, are a popular solution to satisfy the design constraints (such as cost, performance, flexibility, reliability etc.) of such systems. Key challenges in the design of programmable platforms include compiler-in-loop design space exploration (DSE), and automatic generation of software toolkit for hardware/software co-design.
A language-based model of the processor-memory subsystem has several benefits: it serves as a golden reference model for all principals involved in the design; it can be used to drive DSE and automatic software toolkit generation; it can be used to perform top-down (formal) verification and validation; and, it can be refined down to implementation (register-transfer level). In this dissertation, we present EXPRESSION, an architecture description language (ADL) that is designed for DSE of processor-memory sub-system and automatic generation of software toolkit including compiler and cycle-accurate simulator. EXPRESSION has been used to describe various processors from RISC (DLX, MIPS R4000, ARM 9), VLIW (TI C6x), DSP (ST100), etc. Our EXPRESSION based DSE methodology permits exploration of a wide range of processor architectures, and includes compiler-in-loop for accurate analysis of each design configuration.
To aid compiler-in-loop DSE, we developed EXPRESS, a retargetable, instruction level parallelizing compiler that accepts programs in “C” and produces assembly code for the target processor described in EXPRESSION. The EXPRESS compiler is capable of handling irregular architectures, and can adapt to changes in the processor’s instruction-set or micro-architecture. EXPRESS also includes a framework for dynamic customization of the compiler based on the target application and architecture characteristics. These capabilities of EXPRESS make it ideal for use in the DSE of processor-memory subsystems.
Retargetable compilers suffer from the drawback of poor output code quality as compared to a compiler that is “hand-crafted” for the target processor. Key differences between the two compilers include the presence of target specific optimizations and custom phase ordering of optimization passes in the target specific compiler. In this dissertation, we propose a framework, called TransMutations, that enables dynamic, run-time customization of a retargetable compiler. It allows for easy integration of optimizations (called mutations) into the compiler and solves the phase ordering problem by applying optimizations in a context-sensitive manner for each region of the application code. The TransMutations framework has been implemented in the EXPRESS compiler and we present results demonstrating the effectiveness of the technique. This framework improves the quality of code generated by retargetable compilers and enables them to be used in accurate compiler-in-loop DSE of programmable embedded systems.