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Automatic Generation and Verification of Transaction Level Models

June 18, 2009 @ 3:00 pm - 4:00 pm PDT

Automatic Generation and Verification of Transaction Level Models

by Lochi Yu

Location: ET 331

Date and Time: June 18, 2009 10:00am

Professor Daniel Gajski (Chair)
Professor Rainer Doemer
Professor Ian Harris

The rising complexity in system designs over the past decades poses great challenges to current designers. One way to cope with this challenge has been to raise the level of abstraction of design, reducing the number of elements and speeding up design decisions. Transaction Level Models (TLM) have emerged as a new alternative to design Multi-Processor System-on-Chips (MPSoC). TLMs express communication among modules at the transaction level, without simulating the dozens of individual signals in communication elements such as busses. Nevertheless, several drawbacks exist: TLMs are fast, but their accuracy is low, TLMs are being coded manually, often by the use of a System Level Design Language (SLDL), there is no widely-adopted and tool-supported TLM style, and there has been little work on verifi cation at the System Level. In this dissertation, we aimed to contribute in different aspects: We defined a modeling style for SystemC TLMs whose modules have a one-to-one relationship with actual synthesized modules in a FPGA. Then, we defined a data structure, complete and flexible enough to describe a complete embedded system, its hardware platform and application, and developed generation algorithms that would use it to automatically produce an executable TLM in SystemC. Fourth, we designed new transformation rules for models in Model Algebra (MA) that allows veri cation on pipelined models in MA. With our approach, we can have automatic generation and verification of Transaction Level Models, freeing the designer from error-prone manual coding, and allows him to focus on higher level design decisions, speeding up the overall design phase.


June 18, 2009
3:00 pm - 4:00 pm PDT
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