Loading Events

« All Events

  • This event has passed.

Transducer Synthesis for Heterogeneous Multi-processor Systems

July 9, 2009 @ 3:00 pm - 4:00 pm PDT

Transducer Synthesis for Heterogeneous Multi-processor Systems

by Hansu Cho

Location: EH 2210

Date and Time: July 9, 2009, 8:30 AM

Professor Daniel Gajski (Chair)
Professor Rainer Doemer
Professor Ian Harris

Contemporary system design requires more computational power than ever. To overcome this problem, MPSoC is widely used, but design complexity have been increased rapidly. Meanwhile, short time to market forced system designer to reduce development time. Therefore, designer raised the level of abstraction into the higher level called transaction level. But, current high level synthesis tools are dedicated to computational components only. To our best knowledge, there is no synthesis tool for communication components from the transaction level model down to RTL model. In this dissertation, we present a component called transducer which can handle heterogeneous MPSoC communication with multiple buses. Also, we presents a tool for automatic synthesis of transducer. The tool captures the communication parameters in the platform at transaction level and generates transducer in RTL. The design and configuration of the transducer depend on several platform components including heterogeneity of the components, traffic on the bus, size of messages and so on. We define these parameters and show how the synthesizable RTL code for the transducer can be automatically derived based on these parameters.

The advantage of this approach is that the user may modifies transducer parameters to suit specific optimization goals. In contrast to conventional approaches like IP wrappers, our approach enables the user to generate an application specific interface between any number of buses for any platform configuration. Therefore, the system designer is not bound to a set of IPs or protocols for their platform definition. Furthermore, due to automatic generation, we provide several orders of magnitude savings in interface development cost. We demonstrate the synthesizability and quality of our automatically generated transducers using Xilinx ISE tools and FPGA board. We use industrial strength design drivers such as an MP3 decoder and JPEG encoder to test our automatically generated transducers for a variety of platforms and compare them to manually designed transducers on different quality metrics. Our experimental results show that performance of automatically generated transducers are within 5% of manual design for simple platforms but surpasses them for more complex platforms. The area and RTL code size is consistently better than manual design while giving 20X of improvement in development time.


July 9, 2009
3:00 pm - 4:00 pm PDT
Event Category: