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Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design

May 4, 2009 @ 3:00 pm - 4:00 pm PDT

Ultra Low-Power VLSI through Co-Optimization of Architecture and Circuit-Level Design


Speaker Dr. Hiroshi Nakamura
University of Tokyo, Japan
CECS Host Professor Nikil Dutt
Location Donald Bren Hall (DBH) 3011
Date & Time May 4, 2009
Refreshments at 1:30 pm, Lecture begins at 2:00pm (Lecture Cancelled)
Abstract We are currently conducting a research project called ‘Innovative Power Control for Ultra Low-Power and High-Performance System LSIs’ supported by JST (Japan Science and Technology Agency). In this talk, we first briefly introduce the project, and then present a fine grain power gating processor which is currently under development. Fine grain power gating is a promising way to reduce leakage power. However, applying fine grain power gating at very close intervals suffers from energy overhead caused by power gating itself. To overcome this problem, co-optimization between architecture and circuit-level design is important. We will present several techniques about this issue and discuss the experimental results.

Hiroshi Nakamura received the BE, ME, and Ph.D. degree in Electrical Engineering from the University of Tokyo in 1985, 1987, and 1990, respectively. From 1990 to 1996, he was a faculty of Institute of Information Sciences and Engineering at University of Tsukuba. He was a visiting associate professor at the University of California, Irvine from 1996 to 1997. He is currently an Associate Professor of Department of Information Physics and Computing at the University of Tokyo. His research interests include high-performance and low-power processor architecture, VLSI design, and dependable computing. He received the best paper award from IPSJ (Information Processing Society of Japan) in 1994 and Sakai Special Researcher Award from IPSJ in 2002.


May 4, 2009
3:00 pm - 4:00 pm PDT
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