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Foreword Session 1: Resiliency StageNetSlice: A Reconfigurable Microarchitecture Building Block for Resilient CMP Systems (Page 1) A Light-weight Cache-based Fault Detection and Checkpointing Scheme for MPSoCs Enabling Relaxed Execution Synchronization (Page 11) Keynote ZebraNet and Beyond: Applications and Systems Support for Mobile, Dynamic Networks (Page 21) Session 2: Compiler Hardware Interaction Non-Intrusive Dynamic Application Profiler for Detailed Loop Execution Characterization (Page 23) Exploring and Predicting the Architecture/Optimising Compiler Co-Design Space (Page 31) |
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Session 3: Reconfigurable Computing Optimus: Efficient Realization of Streaming Applications on FPGAs (Page 41) Compiling Custom Instructions onto Expression-Grained Reconfigurable Architectures (Page 51) VESPA: Portable, Scalable, and Flexible FPGA-Based Vector Processors (Page 61) Dynamic Coprocessor Management for FPGA-Enhanced Compute Platforms (Page 71) Keynote Power on Demand for Mobile Computing Devices (Page 79) |
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Session 4: Multiprocessors Efficiency and Scalability of Barrier Synchronization on NoC Based Many-core Architectures (Page 81) Decoupled Root Scanning in Multi-Processor Systems (Page 91) SoC-C: Efficient Programming Abstractions for Heterogeneous Multicore Systems on Chip (Page 99) Session 5: Caching and Its Impact Reducing Pressure in Bounded DBT Code Caches (Page 109) Efficient Code Caching to Improve Performance and Energy Consumption for Java Applications (Page 119) Cache-aware Cross-profiling for Java Processors (Page 127) Predictable Programming on a Precision Timed Architecture (Page 137) |
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Session 6: Compilers Advanced Conservative and Optimistic Register Coalescing (Page 147) Control Flow Optimization in Loops using Interval Analysis (Page 157) Efficient Vectorization of SIMD Programs with Non-aligned and Irregular Data Access Hardware (Page 167) Comprehensive Isomorphic Subtree Enumeration (Page 177) Session 7: Power, Reconfigurability, and Simulation Highly
Energy and Performance Efficient Embedded Computing through Approximately
Correct Arithmetic: A Mathematical Foundation and Preliminary Experimental
Validation (Page
187) Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in Embedded Processors (Page 197) Design Space Exploration for Field Programmable Compressor Trees (Page 207) Multi-granularity Sampling for Simulating Concurrent Heterogeneous Applications (Page 217) |
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Session 8: Energy, Power, and Security Active Control and Digital Rights Management of Integrated Circuit IP Cores (Page 227) A Low-Power Parallel Design of Discrete Wavelet Transform using Subthreshold Voltage Technology (Page 235) Power Management of MEMS-Based Storage Devices for Mobile Systems (Page 245) Execution Context Optimization for Disk Energy (Page 255)
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