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Conference Proceedings

39th Design Automation Conference

S. Gupta, T. Kam, S. Rotem, N. Savoiu, N. Dutt, R. Gupta, and A. Nicolau, “Coordinated Transformations for High-Level Synthesis of High Performance Microprocessor Blocks,” 39th Design Automation Conference, pp 898-903, New Orleans, LA, June 2002 download pdf

R. Lysecky, S. Cotterell, and F. Vahid, “A Fast On-Chip Profiler Memory,” 39th Design Automation Conference, pp 28-33, New Orleans, LA, June 2002 download pdf

International Symposium on System Synthesis

S. Cotterell and F. Vahid, “Tuning of Loop Cache Architectures to Programs in Embedded System Designs,” International Symposium on System Synthesis, pp 8-13, Kyoto, Japan, October 2002 download pdf

A. Gerstlauer and D. Gajski, “System-Level Abstraction Semantics,” International Symposium on System Synthesis, pp 231-236, Kyoto, Japan, October 2002 download pdf

S. Gupta, M. Reshadi, N. Saviou, N. Dutt, and A. Nicolau, “Dynamic Common Sub-Expression Elimination During Scheduling in High-Level Synthesis,” International Symposium on System Synthesis, pp 261-266, Kyoto, Japan, October 2002 download pdf

J. Liu, P. H. Chou, and N. Bagherzadeh, “Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors,” International Symposium on System Synthesis, pp 14-19, Kyoto, Japan, October 2002 download pdf

M. Mamidipaka, N. Dutt, and D. Hirschberg, “Efficient Power Reduction Techniques for Time Multiplexed Address Buses,” International Symposium on System Synthesis, pp 207-212, Kyoto, Japan, October 2002 download pdf

W. Mueller, R. Doemer, and A. Gerstlauer, “The Formal Execution Semantics of SpecC,” International Symposium on System Synthesis, pp 150-155, Kyoto, Japan, October 2002 download pdf

J. Peng and D. Gajski, “Optimal Message Passing for Data Coherency in Distributed Architecture,” International Symposium on System Synthesis, pp 20-25, Kyoto, Japan, October 2002 download pdf

P. Petrov and A. Orailoglu, “Low-Power Data Memory Communication for Application-Specific Embedded Processors,” International Symposium on System Synthesis, pp 219-224, Kyoto, Japan, October 2002 download pdf

N. Saviou, S. K. Shukla, and R. Gupta, “Efficient Simulation of Synthesis-Oriented System Level Designs,” International Symposium on System Synthesis, pp 168-173, Kyoto, Japan, October 2002 download pdf

IEEE/ACM International Conference on Computer-Aided Design

S. Cotterell and F. Vahid, “Synthesis of Customized Loop Caches for Core-Based Embedded Systems,” IEEE/ACM International Conference on Computer-Aided Design, pp 655-662, San Jose, CA, November 2002 download pdf

J. Lee, K. Choi, and N. Dutt, “Efficient Instruction Encoding for Automatic Instruction Set Design of Configurable ASIPS,” IEEE/ACM International Conference on Computer-Aided Design, pp 649-654, San Jose, CA, November 2002 download pdf

O. Sinanoglu and A. Orailoglu, “A Novel Scan Architecture for Power-Efficient, Rapid Test,” IEEE/ACM International Conference on Computer-Aided Design, pp 299-303, San Jose, CA, November 2002 download pdf

G. Stitt and F. Vahid, “Hardware/Software Partitioning of Software Binaries,” IEEE/ACM International Conference on Computer-Aided Design, pp 164-170, San Jose, CA, November 2002 download pdf

Design, Automation and Test in Europe Conference

A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, and A. Nicolau, “Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints,” Design, Automation and Test in Europe Conference, pp 168-175, Paris, France, March 2002 download pdf

I. Bayraktaroglu and A. Orailodlu, “Gate Level Fault Diagnosis in Scan-Based BIST,” Design, Automation and Test in Europe Conference, pp 376-381, Paris, France, March 2002 download pdf

E. Cota, L. Carro, A. Orailoglu, and M. Lubaszewski, “Test Planning and Design Space Exploration in a Core-Based Environment,” Design, Automation and Test in Europe Conference, pp 478-485, Paris, France, March 2002 download pdf

F. Doucet, S. Shukla, R. Gupta, and M. Otsuka, “An Environment for Dynamic Component Composition for Efficient Co-Design,” Design, Automation and Test in Europe Conference, pp 736-743, Paris, France, March 2002 download pdf

P. Grun, N. Dutt, and A. Nicolau, “Memory System Connectivity Exploration,” Design, Automation and Test in Europe Conference, pp 894-901, Paris, France, March 2002
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A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau, “An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Widths ISAs,” Design, Automation and Test in Europe Conference, pp 402-408, Paris, France, March 2002 download pdf

S. Irani, S. Shukla, and R. Gupta, “Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Saving States,” Design, Automation and Test in Europe Conference, pp 117-123, Paris, France, March 2002 download pdf

P. Mishra, H. Tomiyama, N. Dutt, and A. Nicolau, “Automatic Verification of In-Order Execution in Microprocessors with Fragmented Pipelines and Multicycle Functional Units,” Design, Automation and Test in Europe Conference, pp 36-43, Paris, France, March 2002 download pdf

P. Petrov and A. Orailoglu, “Power Efficient Embedded Processor IP’s Through Application-Specific Tag Compression in Data Caches,” Design, Automation and Test in Europe Conference, pp 1065-1071, Paris, France, March 2002 download pdf

S. Reda and A. Orailoglu, “Reducing Test Application Time Through Test Data Mutation Encoding,” Design, Automation and Test in Europe Conference, pp 387-393, Paris, France, March 2002 download pdf

M. Sánchez-Élez, M. Férnandez, R. Maestre, R. Hermida, N. Bagherzadeh, and F. Kurdahi, “A Complete Data Scheduler for Multi-Context Reconfigurable Architectures,” Design, Automation and Test in Europe Conference, pp 547-552, Paris, France, March 2002 download pdf

N. Savoiu, S. Shukla, and R. Gupta, “Automatic Concurrency Re-assignment in High Level System Models for Efficient System-Level Simulation,” Design, Automation and Test in Europe Conference, pp 875-881, Paris, France, March 2002 download pdf

W. Tang, R. Gupta, and A. Nicolau, “Power Savings in Embedded Processors Through Decode Filter Cache,” Design, Automation and Test in Europe Conference, pp 443-448, Paris, France, March 2002 download pdf

ASP-DAC/VLSI Design 2002

D. Li, P. Chou, and N. Bagherzadeh, “Mode Selection and Mode Dependency Modeling for Power-Aware Embedded Systems,” 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002), pp 697-704, Bangalore, India, January 2002 download pdf

P. Mishra, H. Tomiyama, A. Halambi, P. Grun, N. Dutt, and A. Nicolau, “Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language,” 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002), pp 458-463, Bangalore, India, January 2002 download pdf

J. Peng, S. Abdi, and D. Gajski, “Automatic Model Refinement for Fast Architecture Exploration,” 7th Asia and South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC/VLSI Design 2002), pp 332-337, Bangalore, India, January 2002 download pdf

HLDVT

P. Mishra, N. Dutt, and A. Nicolau, “Automatic Validation of Pipeline Specifications,” 6th IEEE International Workshop on High Level Design Validation and Test (HLDVT), pp 9-13, Monterey, CA, November 2001

ISSS

P. Mishra, N. Dutt, and A. Nicolau, “Functional Abstraction Driven Design Space Exploration of Heterogeneous Programmable Architectures,” 14th International Symposium on System Synthesis (ISSS), pp 256-261, Montreal, Canada, October 2001

SASIMI

P. Mishra, F. Rousseau, N. Dutt, and A. Nicolau, “Architecture Description Language Driven Design Space Exploration in the Presence of Coprocessors,” 10th Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), Nara, Japan, October 2001

COLP’01

P. D’Alberto, A. Nicolau, A. Veidenbaum, and R. Gupta, “Static Analysis of Parameterized Loop Nests for Energy Efficient Use of Data Caches,” Second Workshop on Compilers and Operating Systems for Low Power (COLP’01), pp 11.1—11.7, Barcellona, Spain, September 2001

ISLPED-01

M. Mamidipaka, D. Hirschberg, and N. Dutt, “Low Power Address Encoding Using Self-Organizing Lists,” ISLPED-01, August 2001