Conference Proceedings

International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

Date:  October 9-14, 2011
Location: Taipei, Taiwan
Website: http://esweek.acm.org/esweek2011/codesisss/

L. Bathen, D. Shin, S-S. Lim, N. Dutt, “SPMVisor: Dynamic ScratchPad Memory Virtualization for Secure, Low Power and High Performance, Distributed On-Chip Memories” CODES+ISSS 2011:79-88 (Best Paper Candidate)

Shahin Golshan, Amin Khajeh, Houman Homayoun, Eli Bozorgzadeh, Ahmed Eltaweel and Fadi Kurdahi, “Reliability-Aware Placement in SRAM-Based FPGA for Voltage Scaling Realization in the Presence of Process Variations,” CODES+ISSS 2011:257-266

Garo Bournoutian and Alex Orailoglu, “Dynamic, Multi-Core Cache Coherence Architecture for Power-Sensitive Mobile Processors,” CODES+ISSS 2011:89-98

A. BanaiyanMofrad, H. Homayoun, and N. Dutt, “FFT-Cache: A Flexible Fault-Tolerant Cache Architecture for Ultra Low Power Voltage Operation,” CODE+ISSS 2011:95-104

International Symposium on Low Power Electronics and Design (ISLPED)

Date: August 1-3, 2011
Location: Fukuoka, Japan
Website: http://www.islped.org/2011/

Sehwan Kim and Pai H. Chou,”Energy Harvesting by Sweeping Voltage-Escaladed Charging of a Reconfigurable Supercapacitor Array,” ISLPED 2011:235-240

D. Dondi, P. Zappi, T. Rosing,”A Scheduling Algorithm for Consistent Monitoring Results with Solar Powered High-performance Wireless Embedded Systems,” ISLPED 2011:259-264

R. Ayoub, U. Ogras, E. Gorbatov, Y. Jin, T. Kam, P. Diefenbaugh, T. Rosing, “OS-level Power Minimization Under Tight Performance Constraints in General Purpose Systems,” ISLPED 2011:321-326

The 48th Design Automation Conference (DAC)

Date: June 5-9, 2011
Location:  San Diego, CA, USA
Website: http://www.dac.com/dac+2011.aspx

Leon Stok, Nikil D. Dutt, Soha Hassoun (Eds.): Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011. ACM 2011, ISBN 978-1-4503-0636-2

Mingjing Chen, Alex Orailoglu, “Diagnosing Scan Clock Delay Faults through Statistical Timing Pruning,” DAC 2011:423-428

Design, Automation and Test in Europe Conference (DATE)

Date: March 2011
Location: Grenoble, France
Website: http://www.date-conference.com/date11/

Lan S. Bai, Robert P. Dick, Peter A. Dinda, and Pai H. Chou, “Simplified Programming of Faulty Sensor Networks via Code Transformation and Run-Time Interval Computation,” DATE 2011:88-93

Lan S. Bai, Robert P. Dick, Pai H. Chou, Peter A. Dinda, “Automated Construction of Fast and Accurate System-Level Models For Wireless Sensor Networks,” DATE 2011:1083-1088

Chengmo Yang, Alex Orailoglu, “Frugal but Flexible Multicore Topologies in Support of Resource Variation-Driven Adaptively,” DATE 2011:1255-1260

Mingjing Chen, Alex Orailoglu, “Diagnosing Scan Chain Timing Faults through Statistical Feature Analysis of Scan Images,” DATE 2011:185-190

Tiantian Liu, Alex Orailoglu, Chun Jason Xue, Minming Li, “Register Allocation for Simultaneous Reduction of Energy and Peak Temperature on Registers,” DATE 2011:20-25

Y. Agarwal, T. Wang and R. Gupta, “Understanding the Role of Buildings in a Smart Microgrid,” DATE 2011:1124-1129

B. Arslan, A. Orailoglu, “Adaptive Test Optimization through Real Time Learning of Test Effectiveness,” DATE 2011:1430-1435

Luis Angel D. Bathen, Nikil D. Dutt, “E-RoC: Embedded RAIDs-on-Chip for Low Power Distributed Dynamically Managed Reliable Memories,” DATE 2011:1141-1146

Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil Dutt, “Slack-aware Scheduling on Coarse Grained Reconfigurable Arrays,” DATE 2011:1513-1516