International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

Date:  October 9-14, 2011
Location: Taipei, Taiwan
Website: http://esweek.acm.org/esweek2011/codesisss/

L. Bathen, D. Shin, S-S. Lim, N. Dutt, “SPMVisor: Dynamic ScratchPad Memory Virtualization for Secure, Low Power and High Performance, Distributed On-Chip Memories” CODES+ISSS 2011:79-88 (Best Paper Candidate)

Shahin Golshan, Amin Khajeh, Houman Homayoun, Eli Bozorgzadeh, Ahmed Eltaweel and Fadi Kurdahi, “Reliability-Aware Placement in SRAM-Based FPGA for Voltage Scaling Realization in the Presence of Process Variations,” CODES+ISSS 2011:257-266

Garo Bournoutian and Alex Orailoglu, “Dynamic, Multi-Core Cache Coherence Architecture for Power-Sensitive Mobile Processors,” CODES+ISSS 2011:89-98

A. BanaiyanMofrad, H. Homayoun, and N. Dutt, “FFT-Cache: A Flexible Fault-Tolerant Cache Architecture for Ultra Low Power Voltage Operation,” CODE+ISSS 2011:95-104