• Most Excellent Design Award (Microprocessors, Cell Based)
• Special Feature Award (Digital Signal Processing, Full Custom)
• Special Feature Award (Analog and Mixed-Signal Circuits, Full Custom)
• Special Feature Award (Custom Application Specific Circuits, Full Custom/Cell Based)

ASP-DAC'97 Organizing Committee

Isao Shirakawa
Dept. of Information Systems Engineering, Osaka Univ.
2-1 Yamadaoka, Suita, Osaka 565, Japan
tel: +81-6-879-7805
fax: +81-6-875-5902
e-mail: sirakawa@ise.eng.osaka-u.ac.jp

Past General Chair:

Tatsuo Ohtsuki
Dept. of Electronics and Communication
Engineering School of Science and Engineering, Waseda Univ,
3-4-1 Okubo, Shinjuku-ku, Tokyo 169, Japan
tel: +81-3-5286-3387
fax: +81-3-3203-9184
e-mail: ohtsuki@cfi.waseda.ac.jp

Secretaries:

Osamu Karatsu
Advanced LSI Lab., NTT System Electronics Labs., NTT Corp.
3-1 Morinosato Wakamiya, Atsugi, Kanagawa 243-01, Japan
tel: +81-462-40-2400
fax: +81-462-40-4344
e-mail: kara@aecl.ntt.jp

Fumiyasu Hirose
CAD Lab., Fujitsu Labs., Ltd.
4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa 211-88, Japan
tel: +81-44-754-2663
fax: +81-44-754-2664
e-mail: hirose@flab.fujitsu.co.jp

Assistant Secretaries:

Nagisa lshiura
Dept. of Information Systems Engineering, Osaka Univ.
2-1 Yamadaoka, Suita, Osaka 565, Japan
tel: +81-6-879-7806
fax: +81-6-875-5902
e-mail: ishiura@ise.eng.osaka-u.ac.jp

Hitoshi Kitazawa
High Speed Integrated Circuit Lab., NTT System Electronics Labs., NTT Corp.
3-1 Morinosato Wakamiya, Atsugi, Kanagawa 243-01, Japan
tel: +81-462-40-2148
fax: +81-462-40-2162
e-mail: kitazawa@aecl.ntt.jp

Tsuneo Nakata
CAD Lab., Fujitsu Labs., Ltd.
4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa 211-88, Japan
tel: +81-44-754-2663
fax: +81-44-754-2664
e-mail: kitazawa@aecl.ntt.jp

Technical Program Chair:

Takeshi Yoshimura
C & C Research Labs., NEC Corp.
4-1-1 Miyazaki, Miyamae-ku, Kawasaki, Kanagawa 216, Japan
tel: +81-44-856-2132
fax: +81-44-856-2235
e-mail: yoshi@sbl.cl.nec.co.jp

Vice Technical Program Chair:

Hiroto Yasuura
Dept. of Computer Science and Communication Engineering
Graduate School of Information Science and Electrical Engineering
Kyushu Univ.
6-1 Kasuga-koen, Kasuga, Fukuoka 816, Japan
tel: +81-92-583-7620
fax: +81-92-583-1338
e-mail: yasuura@c.csce.kyushu-u.ac.jp

EDA Techno Fair Chair:

Kinya Tabuchi
Corporate Engineering, Manufacturing & Information Systems
Mitsubishi Electric Corp.
2-2-3 Marunouchi, Chiyoda-ku, Tokyo 100, Japan
tel: +81-3-3218-2463
fax: +81-3-3218-2465
e-mail: tabuchi@hon.melco.co.jp

Tutorials Chair:

Masaharu Imai
Dept. of Inforination & Computer Sciences, Osaka Univ.
1-0 Machikaneyama-cho, Toyonaka, Osaka 560, Japan
tel: +81-6-850-6623
fax: +81-6-850-6623
e-mail: imai@ics.es.osaka-u.ac.jp

Finance Chair:

Hiroshi Andou
LSICAD Development Dept., Electronic Devices Group, Logic LSI Div.
Oki Electric Industry Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji, Tokyo 193, Japan
tel: +81-426-62-6190
fax: +81-426-67-8367
e-mail: andou@cad.ed.oki.co.jp

Publicity Chair:

Michiaki Muraoka
Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd.
3-1-1 Yagumo-Nakamachi, Moriguchi, Osaka 570, Japan
tel: +81-6-906-4933
fax: +81-6-906-3851
e-mail: muraoka@vdri.src.mei.co.jp

Publication Chair:

Hiroaki Kunieda
Dept. of Electrical and Electronic Engineering, Tokyo Inst. of Technology
2-12-1 Ookayama, Meguro-ku, Tokyo 152, Japan
tel: +81-3-5734-2574
fax: +81-3-5734-2842
e-mail: kunieda@ss.titech.ac.jp

Audio-Visual Chair:

Masahiro Koyama
Design Automation Dept., System LSI Div., Semiconductor Company,
Sony Corp.
4-14-1 Asahi-cho, Atsugi, Kanagawa 243, Japan
tel: +81-462-30-5341
fax: +81-462-30-6225
e-mail: masahiro@saskg.semicon.sony.co.jp

Local Arrangement Chair:

Goichi Yokomizo
Semiconductor & Integrated Circuits Div., Advanced Device Development Dept., Semiconductor Development Center, Hitachi, Ltd.
1-280 Higashi-koigakubo, Kokubunji, Tokyo 185, Japan
tel: +81-423-23-1111
fax: +81-423-27-7715
e-mail: yokomizo@crl.hitachi.co.jp

Registration Chair:

Takashi Kambe
Dept. 4, Precision Technology Development Center, Sharp Corp.
2613-1 Ichinomoto-cho, Tenri, Nara 632, Japan
tel: +81-7436-5-2531
fax: +81-7436-5-4968
e-mail: kambe@edag.ptdg.sharp.co.jp

Visa Application Assistance Chair:

Tomoyuki Fujita
C & C Research Labs., NEC Corp.
4-1-1 Miyazaki Miyamae-ku, Kawasaki, Kanagawa 216, Japan
tel: +81-44-856-8480
fax: +81-44-856-2235
e-mail: fujitaL@sbl.cl.nec.co.jp

Promotion Chair:

Akinori Nishihara
Dept. of Physical Electronics, Tokyo Inst. of Technology
2-12-1 Ookayama, Meguro-ku, Tokyo 152, Japan
tel: +81-3-5734-2560
fax: +81-3-5734-2909
e-mail: aki@ss.titech.ac.jp

New Business Chair:

Kenji Yoshida
Semiconductor Group, Semiconductor DA & Test Engineering Center, Toshiba Corp.
580-1 Horikawa-cho, Saiwai-ku, Kawasaki, Kanagawa 210, Japan
tel: +81-44-548-2400
fax: +81-44-548-2118
e-mail:kyoshida@eeckhd.eec.toshiba.co.jp

Design Contest Chair:

Shuji Tsukiyama
Dept. of Electrical and Electronic Engineering, Chuo Univ.
1-13-27 Kasuga, Bunkyo-ku, Tokyo 112, Japan
tel: +81-3-3817-1871
fax: +81-3-3817-1847
e-mail: tsuki@elect.chuo-u.ac.jp

IEICE TGVLD Representative:

Hiroaki Kunieda (see Publication Chair)

IEICE TGCAS Representative:

Kenji Kawakita
Micro Computer Software Labs., NEC Corp.
2-11-5 Shibaura, Minato-ku, Tokyo 108, Japan
tel: +81-3-5476-1076
fax: +81-3-5476-1113
e-mail: kawakita@ccs.mt.nec.co.jp
IPSJ SIGDA Chair:

Kenji Yoshida (see New Business Chair)

JIPC Representative:

Tatsuo Hakuta
Circuit Products Planning & Development Dept., Components Company,
Electronic Devices Div., Sony Corp.
Osaki West Technology Center
2-10-14 Osaki, Shinagawa-ku, Tokyo 141, Japan
tel: +81-3-3495-3810
fax: +81-3-3495-3843
e-mail: hakuta@tv.sony.co.jp

DAC Representative:

Fumiyasu Hirose (see Secretaries)

EURO-DAC Representative:

Tokinori Kozawa
Semiconductor Technology Academic Research
Onarimon BN Bldg., 6-16-10 Shinbashi, Minato-ku, Tokyo 105, Japan
tel: +81-3-3436-1250
fax: +81-3-3436-1295
e-mail: kozawa@crl.hitachi.co.jp

Technical Program Committee

Takeshi Yoshimura
C & C Research Labs., NEC Corp.
4-1 -1 Miyazaki, Miyamae-ku, Kawasaki, Kanagawa 216, Japan
tel: +81-44-856-2132
fax: +81-44-856-2235
e-mail: yoshi@sbl.cl.nec.co.jp

Vice Chair:

Hiroto Yasuura
Dept. of Computer Science and Communication Engineering
Graduate School of Information Science and Electrical Engineering
Kyushu Univ.
6-1 Kasuga-koen, Kasuga, Fukuoka 816, Japan
tel: +81-92-583-7620
fax: +81-92-583-1338
e-mail: yasuura@c.csce.kyushu-u.ac.jp

Secretaries:

Kazutoshi Wakabayashi
C & C Research Labs., NEC Corp.
4-1 -1 Miyazaki, Miyamae-ku, Kawasaki, Kanagawa 216, Japan
tel: +81-44-856-2134
fax: +81-44-856-2235
e-mail: wakaba@sbl.cl.nec.co.jp

Nagisa Ishiura Dept. of Information Systems Engineering, Osaka Univ.
2-1 Yamadaoka, Suita, Osaka 565, Japan
tel: +81-6-879-7806
fax: +81-6-875-5902
e-mail: ishiura@ise.eng.osaka-u.ac.jp

Fumiyasu Hirose
CAD Lab., Fujitsu Labs., Ltd.
4-1-1 Kamikodanaka, Nakahara-ku. Kawasaki, Kanagawa 211-88, Japan
tel: +81-44-754-2663
fax: +81-44-754-2664
e-mail: hirose@flab.fujitsu.co.jp

Members:

Hideharu Amano, Keio Univ., Japan
Kurt J. Antreich, Technical Univ. of Munich, Germany
Hideki Asai, Shizuoka Univ., Japan
M. Balakrishnan, Indian Inst. of Technology, Delhi, India
Neil W. Bergmann, Queensland Univ. of Technology, Australia
Jinian Bian, Tsinghua Univ., China
Tapan J. Chakraborty, AT&T U.S.A.
Philip Chan, Hong Kong Univ. of Science and Technology, Hong Kong
Kuang-Chien Chen, Fujitsu Labs. of America, U.S.A.
Yinchao Chen, Hong Kong Polytechnic Univ., Hong Kong
Kwang-Ting (Tim) Cheng, Univ. of California at Santa Barbara, U.S.A.
Ying S. Cheung, Univ. of Hong Kong, Hong Kong
Mely Chen Chi, CCL/ITRI, Taiwan
Chiu-sing Choy, Chinese Univ. of Hong Kong, Hong Kong
Masato Edahiro, NEC, Japan
Kunihiro Fujiyoshi, Japan Advanced Inst. of Science and Technology, Japan
Masahiro Fukui, Matsushita Elec tric Industrial, Japan
Soonhoi Ha, Seoul National Univ., Korea
Kiyoharu Hamaguchi, Osaka Univ., Japan
Reiner W. Hartenstein, Universitaet Kaiserslautern, Germany
Kazumi Hatayama, Hitachi, Japan
Toshihiro Hattori, Hitachi, Japan
Graham R. Hellestrand, Univ. of New South Wales, Australia
John Hillawi, DA Solutions, U.K.
Hiromi Hiraishi, Kyoto Sangyo Univ., Japan
Xianlong Hong, Tsinghua Univ., China
Xue Hongxi, Tsinghua Univ., China
Takashi Hotta, Hitachi, Japan
Alan John Hu, Fujitsu Labs. of America, U.S.A.
Sun-Young Hwang, Sogang Univ., Korea
Mitsuo Ikeda, NTT, Japan
Tomoo Inoue, Nara Inst. of Science and Technology, Japan
Kazuhiko Iwasaki, Tokyo Metropolitan Univ., Japan
Marwan Anwar Jabri, Univ. of Sydney, Australia
David M. Johnstone, Canon Information Systems Research Australia, Australia
Wen-Ben Jone, National Chung-Cheng Univ., Taiwan
Tetsuro Kage, Fujitsu Labs., Japan
Seiji Kajihara, Kyushu Inst. of Technology, Japan
Takashi Kambe, Sharp, Japan
Hiroyuki Kanbara, ASTEM RI, Japan
Kaoru Kawamura, Fujitsu Labs., Japan
Beomsup Kim, KAIST, Korea
Kyung-Ho Kim, Samsung Electronics, Korea
Seok-Yoon Kim, Soong Sil Univ., Korea
Hitoshi Kitazawa, NTT.Japan
Hideaki Kobayashi, Univ. of South Carolina, U.S.A.
Tetsushi Koide, Hiroshima Univ., Japan
Yuji Kukimoto, Univ. of California at Berkeley, U.S.A.
Hiroaki Kunieda, Tokyo Inst. of Technology, Japan
Wolfgang Kunz, Max-Planck-Society, Germany
James B. Kuo, National Taiwan Univ., Taiwan
Feipei Lai, National Taiwan Univ., Taiwan
Chung-Len Lee, National Chiao Tung Univ., Taiwan
Tak-Kwan Lee, Chinese Univ. of Hong Kong, Hong Kong
Howard Luong, Hong Kong Univ. of Science and Technology, Hong Kong
Sharad Malik, Princeton Univ., U.S.A.
Yossi Malka, IBM, U.S.A.
Peter Marwedel, Univ. of Dortmund, Germany
Hiroshi Matsumoto, NEC,Japan
Yusuke Matsunaga, Fujitsu Labs., Japan
Yinghua Min, Chinese Academy of Sciences, China
Shin-ichi Minato, NTT,Japan
Yukiya Miura, Tokyo Metropolitan Univ., Japan
Toshiaki Miyazaki, NTT, Japan
Seijiro Moriyama, Toshiba, Japan
Akira Nagoya, NTT, Japan
Tsuneo Nakata, Fujitsu Labs., Japan
Takashi Nanya, Univ. of Tokyo, Japan
Guo-fu Niu, City Univ. of Hong Kong, Hong Kong
Masahiro Numa, Kobe Univ., Japan
Hiroyuki Ochi, Hiroshima City Univ., Japan
Kiyoshi Oguri, NTT, Japan
Naohisa Ohta, NTT,Japan
Hidetoshi Onodera, Kyoto Univ., Japan
Takao Onoye, Osaka Univ., Japan
Yasushi Ooi, NEC,Japan
Sandee Pagey, Cadence Design Systems India, India
Rubin A. Parekhji, Texas Instruments, India
Young-June Park, Seoul National Univ., Korea
Jan M. Rabaey, Univ. of California at Berkeley, U.S.A.
Takayasu Sakurai, Univ. of Tokyo, Japan
Tsutomu Sasao, Kyushu Inst. of Technology, Japan
Hiroshi Sawada, NTT, Japan
Sanjay Sawant, Quickturn Design Systems, U.S.A.
Wen-Zen Shen, National Chiao Tung Univ., Taiwan
Sunil D. Sherlekar, Silicon Automation Systems, India
Shintaro Shimogori, Fujitsu, Japan
Hyunchul Shin, HanYang Univ., Korea
Yoichi Shiraishi, Gunma Univ., Japan
Toru Shonai, Hitachi, Japan
Mandayam Srivas, SRI International, U.S.A.
Chauchin Su, National Central Univ., Taiwan
Atsushi Takahara, NTT, Japan
Pushan Tang, Fudan Univ., China
Kenji Taniguchi, Osaka Univ., Japan
Masayuki Terai, Mitsubishi Electric, Japan
Nozomu Togawa, Waseda Univ., Japan
Masahiko Toyonaga, Matsushita Electric Industrial, Japan
Chi-ying Tsui, Hong Kong Univ. of Science and Technology, Hong Kong
Akihiro Tsutsui, NTT Japan
Kazuhiro Ueda, Shibaura Inst. of Technology, Japan
Nachiket Urdhwareshe, Silicon Automation Systems, India
Ad J. Van de Goor, Delft Univ. of Technology, Netherlands
G. Venkatesh, Silicon Automation Systems, India
Shin'ichi Wakabayashi, Hiroshima Univ., Japan
Takahiro Watanabe, Yamaguchi Univ., Japan
Yosinori Watanabe, DEC, U.S.A.
Xiaoqing Wen, Akita Univ., Japan
Neil Weste, Macquarie Univ., Australia
C.-K. Wong, Chinese Univ. of Hong Kong, Hong Kong
Hei Wong, City Univ. of Hong Kong, Hong Kong
Allen C.-H. Wu, Tsing Hua Univ., Taiwan
Angus Wu, City Univ. of Hong Kong, Hong Kong
Cheng-Wen Wu, Tsing Hua Univ., Taiwan
Yu-Liang Wu, Chinese Univ. of Hong Kong, Hong Kong
Hans-Joachim Wunderlich, Univ. of Siegen, Germany
Xiaolang Yan, Hangzhou Inst. of Electronics Engineering, China
Zhilian Yang, Tsinghua Univ., China
Chingwei Yeh, National Chung-Cheng Univ., Taiwan
Tokumi Yokohira, Okayama Univ., Japan
Goichi Yokomizo, Hitachi, Japan
Satoshi Yokota, ASTEM RI, Japan
Tomohiro Yoneda, Tokyo Inst. of Technology, Japan

Advisory Board

Tadao Azuma
Vice President, Oki Electric Industry Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji, Tokyo 193, Japan

Toshiro Ito
Managing Director, Mitsubishi Electric Corp.
2-2-3 Marunouchi, Chiyoda-ku, Tokyo 100, Japan

Akinobu Kasami
Executive Director, Toshiba Corp.
1-1-1 Shibaura, Minato-ku, Tokyo 105-01, Japan

Shigeo Misaka
Executive Director, Sharp Corp.
1 Asahi, Daimon-cho, Fukuyama-shi, Hiroshima 721, Japan

Masaharu Nagasawa
Director, Matsushita Electric Industrial Co., Ltd.
1006 Kadoma-shi, Kadoma, Osaka 571, Japan

Hajime Sasaki
Vice President, Japan Electric Corp.
5-7-1 Shiba, Minato-ku, Tokyo 108-01, Japan

Shigeru Sato
President, Fujitsu Labs. Ltd.
4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa 211-88, Japan

Koji Takeda
Managing Director, Hitachi Ltd.
1-5-1 Marunouchi, Chiyoda-ku. Tokyo 100, Japan

Seiichi Watanabe
Director, Sony Corp.
4-14-1 Asahi-cho, Atsugi, Kanagawa 243, Japan

Steering Committee

Tatsuo Ohtsuki
Dept. of Electronics and Communication Engineering
School of Science and Engineering, Waseda Univ.
3-4-1 Okubo, Shinjuku-ku, Tokyo 169, Japan
tel: +81-3-5286-3387
fax: +81-3-3203-9184
e-mail: ohtsuki@ohtsuki.comm.waseda.ac.jp

Vice Chair:

Shuji Tsukiyama
Dept. of Electrical and Electronic Engineering, Chuo Univ.
1-13-27 Kasuga, Bunkyo-ku, Tokyo 112, Japan
tel: +81-3-3817-1871
fax: +81-3-3817-1847
e-mail: tsuki@elect.chuo-u.ac.jp

International Coordination:

Hiroaki Kunieda
Dept. of Electrical and Electronic Engineering, Tokyo Inst. of Technology
2-12-1 Ookayama, Meguro-ku, Tokyo 152, Japan
tel: +81-3-5734-2574
fax: +81-3-5734-2911
e-mail: kunieda@ss.titech.ac.jp

Secretary:

Masao Sato
Dept. of Electronics and Communication Engineering, Waseda Univ.
3-4-1 Okubo, Shinjuku-ku, Tokyo 169, Japan
tel: +81-3-5203-5286
fax: +81-3-3203-9184
e-mail: sato@cfi.waseda.ac.jp

ASP-DAC `97 General Chair:

Isao Shirakawa
Dept. of Information Systems Engineering, Osaka Univ.
2-1 Yamadaoka, Suita, Osaka 565, Japan
tel: +81-6-879-7805
fax: +81-6-875-5902
e-mail: sirakawa@ise.eng.osaka-u.ac.jp

ASP-DAC `97 Secretary:

Osamu Karatsu
Advanced LSI Lab., NTT System Electronics Labs., NTT Corp.
3-1 Morinosato Wakamiya, Atsugi, Kanagawa 243-01, Japan
tel: +81-462-40-2400
fax: +81-462-40-4344
e-mail: kara@aec l.ntt.jp

Fumiyasu Hirose
CAD Lab., Fujitsu Labs., Ltd.
4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa 211-88, Japan
tel: +81-44-754-2663
fax: +81-44-754-2664
e-mail: hirose@flab.fujitsu.co.jp

ASP-DAC `97 Technical Program Chair:

Takeshi Yoshimura
C & C Research Labs., NEC Corp.
4-1-1 Miyazaki, Miyamae-ku, Kawasaki, Kanagawa 216, Japan
tel: +81-44-856-2132
fax: +81-44-856-2235
e-mail: yoshi@sbl.cl.nec.co.jp

IEICE TGCAS Chair:

Kenji Kawakita
Micro Computer Software Labs., NEC Corp.
2-11-5 Shibaura, Minato-ku, Tokyo 108, Japan
tel: +81-3-5476-1076
fax: +81-3-5476-1113
e-mail: kawakita@ccs.mt.nec.co.jp

IEICE TGVLD Chair:

Hiroaki Kunieds (see International Coordination)

IPSJ SIGDA Chair:

Kenji Yoshida
Semiconductor Group, Toshiba Corp.
580-1 Horikawa-cho, Saiwai-ku, Kawasaki, Kanagawa 210, Japan
tel: +81-44-548-2400
fax: +81-44-548-2118
e-mail: kyoshida@eeckhd.eec.toshiba.co.jp

JIPC Representative:

Tatsuo Hakuta
Circuit Products Planning & Development Dept.
Components Company, Electronic Devices Div., Sony Corp.
Osaki West Technology Center
2-10-14 Osaki, Shinagawa-ku, Tokyo 141, Japan
tel: +81-3-3495-3810
fax: +81-3-3495-3843
e-mail: hakuta@tv.sony.co.jp

ACM SIGDA Representative:

James P. Cohoon
Dept. of Computer Science, Univ. of Virginia
Thornton Hall, Charlottesville, VA 22903, U.S.A.
e-mail: cohoon@virginia.edu

IEEE CAS Representative:

Graham R. Hellestrand
School of Computer Science & Engineering, Univ. of New South Wales
Kensington, NSW 2033, Australia
e-mail: g.hellestrand@unsw.edu.au

DAC Representative:

Ellen J. Yoffa
Thomas J. Watson Research Center, IBM Corp.
P.O. Box 218, Rm. 33-109, Yorktown Heights, NY 10598, U.S.A.
e-mail: yoffa@watson.ibm.com

EURO-DAC Representative:

Raul Camposano
Design Environment R&D, Synopsys, Inc.
700 East Middlefield Road Mountain View, CA 94043-4033, U.S.A.
e-mail: raul@synopsys.com

EDA Techno Fair Chair:

Kinya Tabuchi
Corporate Engineering, Manufacturing & Information Systems
Mitsubishi Electric Corp.
2-2-3 Marunouchi, Chiyoda-ku, Tokyo 100, Japan
tel: +81-3-3218-2463
fax: +81-3-3218-2465
e-mail: tabuchi@hon.melco.co.jp

EIAJ EDA TC Representative:

Sagoro Hazama
Electronic Device CAD Div., CAD Group, Fujitsu Ltd.
4-1 -1 Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa 211-88, Japan
tel: +81-44-754-2454
fax: +81-44-754-2577
e-mail: hazama@sfdl.ed.fujitsu.co.jp

Members:

Xian-Long Hong
Dept. of Computer Science and Technology, Tsinghua Univ.
Beijing 100084, China
e-mail: hxl-dcs@mail.tsinghua.edu.cn

Chong-Min Kyung
Dept. of Electrical Engineering, Korea Advanced Inst. of Science & Technology (KAIST)
373-1, Kusong-dong, Yusong-gu, Taejon, 305-701, Korea
e-mail: kyung@eekaist.kaist.ac.kr

Hon-Wai Leong
Dept. of Information Systems & Computer Science, National Univ. of Singapore
Lower Kent Ridge Road, Singapore 119260
e-mail: leonghw@iscs.nus.sg

Youn-Long Steve Lin
Dept. of Computer Science, Tsing Hua Univ.
Hsin-Chu, Taiwan 300
e-mail: ylin@cs.nthu.edu.tw

Sunil D. Sherlekar
Silicon Automation Systems (INDIA) PVT LTD.
3008, 12th B" Main, 8th CrosHAL 2nd Stage Indiranagar
Bangalore-560-008, India
e-mail: sds@gsasi.ernet.in

David Skellern
School of Mathematics, Physics Computing & Electronics, Macquarie Univ.
Sydney, NSW 2109, Australia
e-mail: daves@mpce.mq.edu.au

Omar Wing
Faculty of Engineering, The Chinese Univ. of Hong Kong
Shatin, N.T., Hong Kong
e-mail: owing@ie.cuhk.edu.hk

Qianling Zhang
ASIC & System State Key Lab., Fudan Univ.
220 Handan Road, Shanghai, 200433. China
e-mail: qlzhang@ms.fudan.edu.cn

Toshiro Akino
Semiconductor Research Center, Matsushita Electric Industry Co., Ltd.
3-1-1 Yakumo-Nakamachi, Moriguchi, Osaka 570, Japan
e-mail: akino@vdrl.src.mei.co.jp

Kazuyuki Hirakawa
VLSI Res. and Dev. Center, Electronic Devices Group, Oki Electric Industry Co., Ltd.
550-1 Higashiasakawa-cho Hachioji, Tokyo 193, Japan
e-mail: hirakawa@ed.oki.co.jp

Eisaburo Iwamoto
System LSI Div., Semiconductor Company, Sony Corp.
4-14-1 Asahi-cho, Atsugi, Kanagawa 243, Japan
e-mail: iwamoto@semicon.sony.co.jp

Takashi Kambe
Dept. 4, Precision Technology Development Center, Sharp Corp.
2613-1, Ichinomoto-cho, Tenri, Nara 632, Japan
e-mail: kambe@edag.ptdg.sharp.co.jp

Osamu Karatsu (see ASP-DAC'97 Secretary)

Nobuaki Kawato
Computer Network Systems Lab., Fujitsu Labs. Ltd.
1015 Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa 211, Japan
e-mail: kawato@flab.fujitsu.co.jp

Tokinori Kozawa
Semiconductor Technology Academic Research Center (STARC)
Onarimon BN Build. 5F, 16-10 Shinbashi 6-chome, Minato-ku,
Tokyo 105, Japan
e-mail: kozawa@starc.or.jp

Masami Masuyama
EDA System Development Dept., Seiko Instruments Inc.
8 Nakase 1 -chome, Mihama, Chiba-shi, Chiba 261, Japan
e-mail: masuyama@eda.mk.sii.co.jp

Shinichi Murai
Advanced Electronic Design Automation System LSI Lab.,
Mitsubishi Electric Corp.
4-1 Mizuhara, Itami, Hyogo 664, Japan
e-mail: shinichi@lsi.melco.co.jp

Fusao Wada
R & D Div., Zuken Inc.
2-25-1 Edahigashi, Tsuzuki-ku, Yokohama, Kanagawa 224, Japan
e-mail: f_wada@zuken.co.jp

Kunihiro Asada
Dept. of Electronic Engineering, Univ. of Tokyo
7-3-1, Hongo, Bunkyo-ku, Tokyo 113, Japan
e-mail: asada@silicon.u-tokyo.ac.jp

Hideo Fujiwara
Graduate School of Information Science, Nara Inst. of Science and Technology (NAIST)
Ikoma, Nara 630-01, Japan
e-mail: fujiwara@is.aist-nara.ac.jp

Masaharu Imai Dept. of Information & Computer Sciences, Faculty of Engineering Science, Osaka Univ.
1-3 Machikane-yama, Toyonaka, Osaka 560, Japan
e-mail: imai@ics.es.osaka-u.ac.jp

Michitaka Kameyama
Graduate School of Information Sciences, Tohoku Univ.
Aoba, Aramaki, Aoba-ku, Sendai, Miyagi 980-77, Japan
e-mail: michi@kameyama.ecei.tohoku.ac.jp

Yoshikazu Miyanaga
Div. of Electronics & Information Engrg., Graduate School of Engineering
Kyoto Univ.
Sakyo-ku, Kyoto 606-01, Japan
e-mail: nakamura@kuee.kyoto-u.ac.jp

Hidetoshi Onodera
Dept. of Electronics and Communication
Graduate School of Engineering, Kyoto Univ.
Sakyo-ku, Kyoto 606-01, Japan
e-mail: onodera@tamaru.kuee.kyoto-u.ac.jp

Tsutomu Sasao
Dept. of Computer Science and Electronics, Kyushu Inst. of Technology
680-4 Iizuka, Fukuoka 820, Japan
e-mail: sasao@cse.kyutech.ac.jp

Kazuhiro Ueda
Dept. of Electronic Information Systems, Shibaura Inst. of Technology
307 Fukasaku, Omiya, Saitama 330, Japan
e-mail: ueda@ulab.se.shibaura-it.ac.jp

Shin'ichi Wakabayashi
Faculty of Engineering, Hiroshima Univ.
4-1 Kagamiyama 1-chome, Higashi-Hiroshima, Hiroshima 739, Japan
e-mail: wakaba@ecs.hiroshima-u.ac.jp

Hiroto Yasuura
Dept. of Computer Science and Communication Eng.
Graduate School of Information Science and Electrical Engineering
Kyushu Univ.
6-1 Kasuga-koen, Kasuga, Fukuoka 816, Japan
e-mail: yasuura@c.csce.kyushu-u.ac.jp

General Chair's Message

Thus, at least at present, ASP-DAC should aim to provide the CAD/DA community of this Region with the opportunity to exchange leading edge ideas and concepts on different aspects of sciences and technologies of the upperstream design, as well as on novel methodologies of the downstream design.

The response to the Call for Papers was overwhelming; more than 150 papers covering a wide spectrum of DA activities were submitted. In spite of our best efforts to accommodate all papers, it was necessary for the Technical Program Committee (TPC) to turn down more than a third of the submissions.

The TPC has worked very diligently to put together an outstanding technical program of both regularly contributed and invited sessions. In addition, we have realized production of the University LSI Design Contest for the first time. The contest was designed to encourage academia to enter aggressively into the practice of VLSI implementation so as to cope with the 'design crisis' which is to prevail in our Region.

All together, I predict that ASP-DAC '97 will be a great success. It should provide an ideal setting for renewing friendships, making new acquaintances and participating in an outstanding technical program!

Isao Shirakawa
General Chair, ASP-DAC '97

Program Chair's Message:

The Technical Program Committee was organized into ten groups, each of which was focused on a specific area. Each group was composed of experts from all over the world who were responsible for evaluating and selecting the papers. Thanks to their great efforts, 95 regular and short papers were selected from 154 submissions from 19 countries and were organized into the Technical Program. The Technical Program is structured under four parallel tracks; three Regular Tracks and one Special Track. All the accepted papers and three embedded tutorials are included in the Regular Tracks. Special sessions and panel sessions are incorporated into the Special Track whenever the topics are appropriate. The TPC believes that the high technical standard of the submitted papers reflects the importance of this Conference and its location in the fastest developing area of the high-technology world.

Finally, the TPC would like to thank all authors for their excellent submissions. The works of the authors are what ultimately make ASP-DAC a premier conference for presenting the latest advances in the field of design automation.

Takeshi Yoshimura
Program Chair, ASP-DAC '97

ASP-DAC '97 University LSI Design Contest

Eighteen designs from six countries were submitted to the Contest. Through the peer review by the Design Contest Committee members, thirteen excellent LSI designs were selected, which are presented in the Proceedings. From among these selected designs, the Design Contest Committee decided to confer one Most Excellent Design Award and three Special Feature Awards on the designs listed in the Proceedings. You will see a summary report of the contest in the Proceedings, too.

In selecting designs the following criteria were used: (1) Reliability of design and implementation, (2) Quality of implementation, (3) Performance of the design, (4) Novelty of application, algorithm, architecture, and circuit configuration, (5) Other additional points, such as new design methodology and testability. Unlike usual reviews of technical papers, our evaluation of submitted designs placed more importance on how the LSI circuits were designed and implemented than anything else.

In Session 4D, the thirteen excellent LSI designs selected by the Committee will be presented by posters with short lectures. You also see some implemented LSI chips and a demonstration of a chip. Please come to the Session 4D and enjoy stimulating discussions about LSI design. Demonstration may be seen at EDA Techno Fair, too. It is our hope that this design contest will be of great interest and benefit not only to the people in universities and other educational institutions but also the people in industry, and will further the progress of the education and research of LSI design and implementation.

Shuji Tsukiyama, Design Contest Chair
Kenji Yoshida, Design Contest Vice-Chair and New Business Chair

University LSI Design Contest Committee

Chair:

Shuji Tsukiyama
Dept. Electrical and Electronic Engineering Chuo Univ.
1-13-27 Kasuga, Bunkyo-ku, Tokyo 112, Japan
tel: +81-3-3817-1871
fax: +81-3-3817-1847
e-mail: tsuki@elect.chuo-u.ac.jp

Vice-Chair:

Kenji Yoshida
Semiconductor Group, Semiconductor DA & Test Engineering Center,Toshiba Corp.
580-1 Horikawa-cho, Saiwai-ku, Kawasaki, Kanagawa 210, Japan
tel: +81-44-548-2400
fax: +81-44-548-2118
e-mail: kyoshida@eeckhd.eec.toshiba.co.jp

Secretaries:

Hideharu Amano
Dept. of Electrical Engineering, Keio Univ.
3-14-1 Hiyoshi, Kohoku-ku, Yokohama 223, Japan
tel: +81-45-560-1063
fax: +81-45-560-1064
e-mail: hunga@aa.cs.keio.ac.jp

Takashi Mitsuhashi
Semiconductor DA & Test Engineering Center, Toshiba Corp.
580-1 Horikawa-cho, Saiwai-ku, Kawasaki Kanagawa 210, Japan
tel: +81-44-548-2243
fax: +81-44-548-8306
e-mail: mituhasi@dad.eec.toshiba.co.jp

• Yukio Akazawa, NTT, Japan (Area Chair: Analog/Mixed-Signal)
• Cheong-Fat Chan, The Chinese Univ. of Hong Kong, Hong Kong
• Lian-Gee Chen, National Taiwan Univ., Taiwan
• Tadayoshi Enomoto, Chuo Univ., Japan
• Graham Hellestrand, The Univ. of New South Wales, Australia
• Hiroaki Hirata, Kyoto Inst. of Tech., Japan (Area Chair: Microprocessors)
• Nagisa Ishiura, Osaka Univ., Japan
• Beomsup Kim, KAIST, Korea
• Hitoshi Kitazawa, NTT, Japan
• Noboru Kubo, Sharp Corp., Japan
• Chong-Min Kyung, KAIST, Korea
• S. Madhusudanan, Silicon Automation Systems, India
• Yoshikazu Miyanaga, Hokkaido Univ., Japan (Area Chair: Custom/ASIC)
• Akinori Nishihara, Tokyo Inst. of Tech., Japan (Area Chair: DSP)
• Keisuke Okada, Mitsubishi Electric Corp., Japan
• Yutaka Okada, Hitachi Ltd., Japan
• Jan M. Rabaey, Univ. of California at Berkeley, U.S.A.
• Masao Sato, Waseda Univ., Japan
• Keitaro Sekine, Science Univ. of Tokyo, Japan
• Takashi Taniguchi, Matsushita Elec. Industrial Co., Ltd., Japan
• Chi-Ying Tsui, Univ. of Science and Tech., Hong Kong
• Yoshiaki Umezawa, Oki Electric Industry Co., Ltd., Japan
• Neil Weste, Macquarie Univ., Australia
• Futao Yamaguchi, Sony Corp., Japan
• Kaichi Yamamoto, Sony Corp., Japan
• Yoichi Yano, NEC Corp., Japan
• Koichi Yamashita, Fujitsu Lab. Ltd., Japan
• Hironori Yamauchi, Ritsumeikan Univ., Japan
• Goichi Yokomizo, Hitachi Ltd., Japan
• Jun Yu, Fudan Univ., China

University LSI Design Contest Award Recipients

Most Excellent Design Award (Microprocessors, Cell Based)

"HK386: An x86-Compatible 32bit CISC Microprocessor"

C. M. Kyung, I. C. Park, , K. S. Seong, S. J. Lee, H. Choi, S. R. Maeng, D. T. Kim, J. S. Kim, S. H. Park, Y. J. Kang (Korea Advanced Institute of Science and Technology, Korea), S. K. Hong (Hyundai Electronics Industries, Korea), B. S. Kong (LG Semicon, Korea)

This paper describes a design of a complex processor which is compatible with i386 with respect to the instruction and pin-to-pin levels. The chip contains 400,000 transistors in a 10mmx10mm die, and performs at 20MIPS at 40 MHz, which is quite impressive for an i386 equivalent. Several standard OS's and their application programs are also confirmed to run successfully on the chip. Although this is largely a re-engineering project, the degree of novelty and ingenuity required of first time CPU designers in such a large project is very high. Moreover, the verification methodology is extremely rigorous to ensure compatibility between the designed chip and the commercially available Intel product. These features, as well as the magnitude and complexity of this project, distinguish the design very clearly from the other designs submitted. Thus, this design is worthy of the Most Excellent Design Award.

Special Feature Award (Digital Signal Processing, Full Custom)

"A Functional Memory Type Parallel Processor for Vector Quantization"

K. Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, and K. Tamaru (Department of Electronics and Communication, Graduate School of Engineering, Kyoto University, Japan)

This paper describes a full custom design and implementation of a CAM-based parallel search chip for vector quantization. It accelerates nearest neighbor search which is necessary in vector quantization of images. Distances between an input vector and the reference vectors in a codebook are computed simultaneously in all PEs, and the minimum distance is calculated in parallel. A chip including 4 PEs and some test circuits is fabricated in a reasonably small die area. The design flow is thoughtful and interesting. The chip, operating at 25MHz, can search 152,000 nearest vectors per second. This attractive performance shows that the authors' CAM-based solution has been a good choice. Therefore, this design is worthy of a Special Feature Award.

Special Feature Award (Analog and Mixed-Signal Circuits, Full Custom)

"A 0.8 um CMOS Delayed Locked Loop for VLSI Systems with Sub-500ps Clock Skew"

Y. B. Kim and T. W. Chen (Department of Electrical Engineering, Colorado State University, U.S.A.)

This paper describes a design of a CMOS variable delay line Delay Locked Loop (DLL) circuit, which is aimed at the reduction of clock skew on a large integration system such as DRAM/Logic merged LSIs. In this design, a push-pull type clock synchronization scheme was proposed for reducing the settling time of the loop, and the test IC fabricated by using 0.8 mm CMOS process achieved sub-500-ps skew operation. This skew reduction effect is 1/2 to 1/6, and hence the proposed architecture has great potential for practical use. The achievement was made through the circuit design based on the precise understanding of the requirements for circuit components. Therefore, this design is worthy of a Special Feature Award.

Special Feature Award (Custom Application Specific Circuits, Full Custom/Cell Based)

"A Stand-Alone ASIC for Real-Time Edge Detection"

F. M. Alzahrani and T. W. Chen (Department of Electrical Engineering, Colorado State University, U.S.A.)

This paper describes a new edge detection algorithm for a given image data and a design of a VLSI realizing the algorithm. The components of the proposed algorithm were designed on quite high regular structure, which is suitable to VLSI implementation. A highly efficient pipeline mechanism is introduced in its design, and the novel approach of the simultaneous design in the algorithm and the hardware implementation was used. Accordingly, the edge pixel can be estimated at every clock, and hence the 30 number of images with 640x480 size can be analyzed at only one second by using this chip. These results are recognized as quite important and thus this design is worthy of a Special Feature Award.

Call For Papers

ASP-DAC '98
Asia and South Pacific Design Automation Conference 1998
with EDA TechnoFair '98

Areas of Interest:
Original Papers on, but not limited to, the following areas are invited.

[A] Design Issues---Practice/Experience with DA Tools:

1) Design experience using DA tools,

2) High performance/Low power/Deep submicron design,

3) Rapid prototyping and emulation,

4) Design flows for DSP/Communication/Multi-media systems, 5) CAD for new Devices

[B] Foundations of CAD Technology:

1) Theory of optimization,

2) Fundamental theory of physical design,

3) Logic function and switching theory,

4) Foundation of verification,

5) Formal semantics of HDL's,

6) New theories for CAD

[C] Physical Design:

1) Partitioning,

2) Floorplanning and placement,

3) Global and detailed routing,

4) Module generation,

5) High-speed and microwave DA,

6) Layout verification,

7) PCB design,

8) Packaging CAD,

9) Interaction between logic and layout design

[D] Synthesis:

1) Combinational synthesis,

2) Sequential synthesis,

3) High-level synthesis,

4) HW/SW codesign and system synthesis,

5) Synthesis for high performance/low power systems,

6) Asynchronous synthesis,

7) Mapping and technology dependent optimization

[E] Test:

1) Fault modeling and simulation,

2) Test pattern generation,

3) Design-for-testability,

4) Fault tolerant methods,

5) Test design issues

[F] Design Verification and Simulation:

1) Functional verification,

2) System design verification,

3) Timing verification,

4) Performance analysis,

5) Circuit and timing simulation,

6) Logic and functional simulation,

7) System-level simulation

[G] Technology CAD:

1) Device simulation,

2) Process simulation,

3) Device design optimization,

4) CAD tools for new devices

[H] Analog Design:

1) Circuit analysis,

2) Analog synthesis,

3) Process and device modeling,

4) Memory cell design

[I] Design Methods and Environments:

1) Design scheme, HDL/diagram/chart-based design,

2) Frameworks and databases,

3) Libraries and tools for ASICs,

4) Integration of design tools for ULSI design,

5) Human factors in DA,

6) HW accelerator for DA

[J] Manufacturing:

1) DA for IC fabrication,

2) Computer-aided manufacturing,

3) Multi-chip module: design and manufacturing

[K] Education and Training:

1) Education of VLSI design,

2) Education of CAD technologies,

3) Training course for CAD tools

Sponsored by:(Expected)
IEICE (Institute of Electronics, Information and Communication Engineers)
IPSJ (Information Processing Society of Japan)
ACM SIGDA
IEEE Circuits and Systems Society

Supported by:
EIAJ (Electronics Industries Association of Japan)
STARC (Semiconductor Technology Academic Research Center)

Best Paper Award Candidates

Category 1

1A.1 Co-evaluation of FPGA Architectures and the CAD System for Telecommunication

Tsunemasa Hayashi, NTT System Electronics Laboratories

3A.1 Polling-based Real-time Software for MPEG2 System Protocol LSIs

Jiro Naganuma, NTT System Electronics Laboratories

3A.2 Synthesis and Analysis of an Industrial Embedded Microcontroller

Ing-Jer Huang, Institute of Computer and Information Engineering, National Sun Yat-Sen Univ.

7A.1 Chip Est-FPGA: A Tool for Chip Level Area and Timing Estimation of Lookup Table Based FPGAs for High Level Applications

Min Xu, Department of Information and Computer Science, Univ. of California, Irvine

8A.4 Statistical Design of Macro-models For RT-level Power Evaluation

Qing Wu, EEB 300, Department of Electrical Engineering-Systems, Univ. of Southern California

Category 2

1B.3 Performance and Reliability Driven Clock Scheduling of Sequential Logic Circuits

Atsushi Takahashi, Department of Electrical and Electronic Engineering Tokyo Institute of Technology

3C.1 CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation Environment for Static CMOS Circuits

Jiing-Yuan Lin, Institute of Electronics National Chiao Tung Univ.

5B.1 Testability Analysis Method for Register-Transfer Level Descriptions

Mizuki Takahashi, Precision Technology Development Center SHARP Corporation

9B.1 BDD-based Logic Partitioning for Sequential Circuits

Chung-Kuan Cheng, Department of Computer Science and Engineering, Univ. of California at San Diego

Category 3

7C.2 A New Linear-Time Harmonic Balance Algorithm for Cyclostationary Noise Analysis in RF Circuits

Jaijeet Roychowdhury, Bell Laboratories

8C.2 DP-Gen: A Datapath Generator for Multiple-FPGA Applications

Allen Chung-Hao Wu,Department of Computer Science, Tsing Hua Univ.

8C.4 Not Necessarily More Switches More Routability

Yu Liang Wo,Department of Computer Science and Engineering, The Chinese Univ. of Hong Kong

9C.1 A Mapping from Sequence-Pair to Rectangular Dissection

Hiroshi Murata, Japan Advanced Institute of Science and Technology