Conference Proceedings

Location: Chicago IL
Web Site: http://www.sigda.org/glsvlsi/local2.html

A. Gordon-Ross, F. Vahid, N. Dutt, ” A First Look at the Interplay of Code Reordering and Configurable Caches,” Great Lakes Symposium on VLSI (GLSVLSI), April 2005.download pdf

Location: Jersey City, NY
Web Site: http://www.codes-isss.org/

M. Reshadi, D. Gajski, “A Cycle-Accurate Compilation Algorithm for Custom Pipelined Datapaths,” International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2005.download pdf

A. Shrivastava, E. Earlie, N. Dutt, and A. Nicolau, “Aggregating Processor Free Time for Energy Reduction,” International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2005.download pdf

D. Shin, A. Gerstlauer, R. Dömer, and D. Gajski, “Automatic Network Generation for System-on-Chip Communication Design,” International Conference on Hardware/Software Codesign and System Synthesis, September 2005.download pdf

Location: Portland, OR
Web Site: http://www.chi2005.org/

S. Cotterell and F. Vahid, “A Logic Block Enabling Logic Configuration by Non-Experts in Sensor Networks,” Conference on Human Factors in Computing (CHI), April 2005.download pdf

Location: San Jose, CA
Web Site: http://www.iccd-conference.org/

M. Reshadi, B. Gorjiara, D. Gajski, “Utilizing Horizontal and Vertical Parallelism with No-Instruction-Set Compiler for Custom Datapaths,” International Conference on Computer Design (ICCD), October 2005.download pdf

M. Ramirez, A. Cristal, A. Veidenbaum, L. Villa, M. Valero, “A New Pointer-based Instruction Queue and Its Power-Performance Evaluation,” International Conference on Computer Design (ICCD 2005), October 2005. Best Paper Award at ICCD 2005

Location: Higashikasugano, Japan
Web Site: http://alice.ics.nara-wu.ac.jp/ishpc-VI/

P.D’Alberto and A. Nicolau, “Using Recursion to Boost ATLAS’s Performance,” International Symposium on High Performance Computing (ISHPC-VI), September 2005.download pdf

A. Kejariwal, A. Nicolau and C. Polychronopoulos, “Enhanced Loop Coalescing: A Compiler Technique for Transforming Non-Uniform Iteration Spaces,” International Symposium on High Performance Computing (ISHPC-VI), September 2005.

D. Nicolaescu,  A. Veidenbaum, A. Nicolau, “Using a Way Cache to Improve Performance of Set-Associative Caches,” International Symposium on High Performance Computing (ISHPC-VI), September 2005.

Location: Napa, CA
Web Site: http://www.fccm.org/

S. Banerjee, E. Bozorgzadeh, and N. Dutt, “Considering runtime reconfiguration overhead in Task Graph Transformations for dynamically reconfigurable architectures,” IEEE symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005.

Location: Hong Kong, China

C. Liu and J-L Gaudiot, “Static Partitioning vs Dynamic Sharing of Resources in Simultaneous Multi-Threading Microarchitectures,” International Workshop on Advanced Parallel Programming Technologies (APPT 2005), October 27-28, 2005. download pdf

Location: Hong Kong, China
Web Site: http://www.comp.hkbu.edu.hk/~rtcsa2005/

K. Raman Y. Zhang, M. Panahi, J.A. Colmenares, R. Klefstad, “Patterns and Tools for Achieving Predictability and Performance with Real-Time Java,” IEEE International Conference on Real-Time and Embedded Computing Systems and Applications, August 17- 19, 2005.

Location: Denver, CO

S. Mohapatra, R. Cornea, H. Oh, K. Lee, M. Kim, et al,“A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems,” IPDPS’05 Workshop on NSF Next Generation Software Program, April 2005.download pdf

Location: Irvine, CA

C. Park, P. Chou, and M. Shinozuka, “DuraNode: Wireless Networked Sensor for Structural Health Monitoring,” IEEE International Conference on Sensors, Oct. 31 – Nov. 1, 2005.