Conference Proceedings

Location: Yokohama, Japan
Web Site: http://www.aspdac.com/

B. Gorjiara, M. Reshadi, D. Gajski, “Designing a Custom Architecture for DCT Using NISC Design Flow,” ASP-DAC’06 Design Contest, January 2006.download pdf

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Constraint-Driven Bus Matrix Synthesis for MPSoC,” ASP-DAC’06, January 2006.download pdf

S. Banerjee, E Bozorgzadeh, N. Dutt, ” PARLGRAN: Parallelism Granularity Selection for Scheduling task chains on dynamically reconfigurable architectures,” ASP-DAC’06, January 2006.download pdf

H. Oh, N. Dutt, S. Ha, ” Memory Optimal Single Appearance Schedule wiht Dynamic Loop Count for Synchronous Dataflow Graphs,” ASP-DAC’06, January 2006.download pdf

H. Cho, S. Abdi, D. Gajski, “1D-19: Design and Implementation of a Duplex AMBA-TMS Transducer,” ASP-DAC’06, January 2006.download pdf

Location: Nagoya, Japan
Web Site: http://www.mein.nagoya-u.ac.jp/IEEE-NANO/IEEE-NANO-2005/

T. Nakano, T. Suda, M. Moore, R. Egashira, A. Enomoto, and K. Arima, “Molecular Communication for Nanomachines Using Intercellular Calcium Signaling,” IEEE Conference on Nanotechnology, June 11-15, 2005.download pdf

Location: Monterey, CA
Web Site: http://isfpga.cs.caltech.edu/

S. Sivaswamy, G. Wang, C. Ababei, K. Bazargan, R.Kastner, and E. Bozorgzadeh, “HARP:Hard-wired Routing Pattern FPGAs,”  ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2005. download pdf

G. Stitt, Z. Guo, F. Vahid, and W. Najjar, “Techniques for Synthesizing Binaries to an Advanced Register/Memory Structure,” ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2005. download pdf

Location: Beijing, China
Web Site:http://www.ict.ac.cn/hpcasia2005/

P.D’Alberto and A. Nicolau, “Adaptive Strassen and ATLAS’s DGEMM: A Fast Square-Matrix Multiply for Modern High-Performance Systems,” International Conference on High Performance Computing in Asia Pacific Region (HPC Asia), November 30-December 3, 2005. download pdf

Location: Samos, Greece
Web Site: http://www.ece.uvic.ca/asap2005/

S. Pasricha, N. Dutt, M. Ben-Romdhane, “Using TLM for Exploring Bus-based SoC Communication Architectures,” International Conference on Application-specific Systems, Architectures and Processors (IEEE ASAP 2005), July 2005.download pdf

Location: New Orleans, LO
Web Site: http://www.scs.org/confernc/westernsim/westernsim05/cfp/icsie05.htm

A. Cristobal-Salas, J-L. Gaudiot, C. Jauregui-Romo, E. Herran-Paz, and A. Rodriguez-Daz, “Blood Circulation Simulation Using a Distributed Decentralized-control Design,” International Conference on Simualtion in Education (IC-SiE 2005), January 23-27, 2005.

Location: Nagasaki, Japan
Web Site: http://euc05.euc-conference.org/

J. Lu, L. Bao and T. Suda, “Coverage aware Sensor Engagement in Dense Sensor Networks,” IFIP International Conference on Embedded and Ubiquitous Computing, December 6-9, 2005. download pdf

Location: San Jose, CA
Web Site: http://www.collaboratecom.org/2005/

R. Egashira, A. Enomoto, T. Suda, H. Sasaki, and H. Iwasaki, “Distributed Service Discovery using Preference,” CollaborateCom 2005, December 19-21, 2005.

Location: Cambridge, MA
Website: http://ics05.csail.mit.edu/

R. Gonzales, A. Cristal, A. Veidenmbaum., and M. Valero, “An Asymmetric Clustered Processor based on Value Content,” ACM International Conference on Supercomputing (ICS 2005), June 2005.

Location: Shanghai, China
Web Site: http://www.aspdac.com/

S. Abdi and D. Gajski, “A Formalism for Functionality Preserving System Level Transformations,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 139-144, January 18-21, 2005 download pdf

Y. Agarwal, C. Schurgers, and R. Gupta, “Dynamic Power Management Using On-Demand Paging for Networked Embedded Systems,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 755-759, January 18-21, 2005 download pdf

R. Ayoub and A. Orailoglu, ” A Unified Transformational Approach for Reductions in Fault Vulnerability, Power, and Crosstalk Noise and Delay on Processor Buses,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 729-734, January 18-21, 2005 download pdf

L. Cai, A. Gerstlauer,  and D. Gajski, “Multi-Metric and Multi-Entity Characterization of Applications for Early System Design Exploration,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 944-947, January 18-21, 2005 download pdf

A. Gerstlauer, D. Shin, R. Doemer, and D. Gajski, “System-Level Communication Modeling for Network-on-Chip Synthesis,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 45-48, January 18-21, 2005 download pdf

S. Pasricha, N. Dutt, and M. Ben-Romdhane, “Automated Throughput-Driven Synthesis of Bus-Based Communication Architectures,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 495-498, January 18-21, 2005 download pdf

J. Peng, S. Abdi, and D. Gajski, “A Clustering Technique to Optimize hardware/Software Synchronization,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 965-968, January 18-21, 2005 download pdf

W. Rao, A. Orailoglu, and R. Karri, “Fault Tolerant Nanoelectronic Processor Architectures,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 311-316, January 18-21, 2005 download pdf

J. Seo and N. Dutt, “A Generalized Technique for Energy-Efficient Operating Voltage Set-Up in Dynamic Voltage Scaled Processors,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 836-841, January 18-21, 2005 download pdf

R. Topaloglu and A. Orailoglu, “Forward Discrete Probability Propagation Method for Device Performance Characterization Under Process Variations,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 220-223, January 18-21, 2005 download pdf

S. Verma, K. Ramineni, and I. Harris, “An Efficient Control-Oriented Coverage Metric,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 317-322, January 18-21, 2005 download pdf
T. Wei, K. Wu, R. Karri, and A. Orailoglu, “Fault Tolerant Quantum Cellular Array (QCA) Design Using Triple Modular Redundancy with Shifted Operands,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 1192-1195, January 18-21, 2005 download pdf

C. Zhang and F. Kurdahi, “On Combining Iteration Space Tiling with Data Space Tiling for Scratch-Pad Memory Systems,” Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Shanghai, China, pp 965-968, January 18-21, 2005 download pdf