Conference Proceedings

Location: Seoul, Korea
Website: http://www.aspdac.com/

S. Pasricha, N. Dutt, “ORB: An On-chip Optical Ring Bus Communication Architecture for Multi-Processor Systems-on-Chip,” IEEE Asia & South Pacific Design Automation Conference (ASPDAC 2008), Seoul, Korea, January 2008.

Gunar Schirner, Andreas Gerstlauer, Rainer Doemer, “Automatic Generation of Hardware dependent Software for MPSoCs from Abstract System Specifications,” Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, January 2008.

Love Singhal, Sejong Oh and Eli Bozorgzadeh, “Statistical Power Profile Correlation for Realistic Thermal Estimation,” IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, January 2008.

A. Shrivastava, I. Issenin , N. Dutt, “A Compiler-in-the-Loop Framework to Explore Horizontally Partitioned Cache Architectures,” Proceedings of ASPDAC-2008, January 2008.

N. Dutt, “Quo Vadis, BTSoCs (Billion Transistor SoCs)?” Panel Position Statement, Proceedings of ASPDAC-2008, January 2008.

Location: Squaw Creek, Lake Tahoe, CA
Website: http://iccd.et.tudelft.nl/

Houman Homayoun, Alex Veidenbaum and Jean-Luc Gaudiot, “Adaptive Techniques for Leakage Power Management in L2 Cache Peripheral Circuits,” Proc. IEEE International Conference on Computer Design, ICCD, 2008.

Houman Homayoun, Mohammad Makhzan and Alex Veidenbaum, ZZ-HVS, “Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits,” Proc. IEEE International Conference on Computer Design, ICCD, 2008.

Location: HICC, Hyderabad, India
Website: http://www.vlsiconference.com/vlsi2008/

S. Pasricha, Y. Park, S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, “Incorporating PVT Variations in System-level Power Exploration of On-Chip Communication Architectures,” IEEE VLSI Design Conference (VLSID 2008), Bangalore, India, January 2008.

D. Kannan, A. Gupta, A. Shrivastava, N. Dutt, and F. Kurdahi, “PTSMT: A Tool for Cross-Level Power, Performance and Temperature Exploration of SMT Processors,” Proceedings of the 2008 International Conference on VLSI Design, Hyderabad, India, January, 2008.

Location: KaoHsiung, Taiwan
Website: http://www.rtcsa.org/

Chongjing Chen and Pai H. Chou, “EcoDAQ: A Case Study of a Densely Distributed Real-Time System for High Data Rate Wireless Data Acquisition,” to appear, in Proc. 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2008. Kaohsiung, Taiwan.

Location: Samos, Greece
Website: http://samos.et.tudelft.nl/samos_viii/

Houman Homayoun, Mohammad Makhzan, Jean-Luc Gaudiot, and Alex Veidenbaum, “A Centralized Cache Miss Driven Technique to Improve Processor Power Dissipation,” International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS VIII.

Location: San Jose, CA
Website: http://www.ieee-cicc.org/

Aminghasem Safarian, Lei Zhou, and Payam Heydari, “A Current-Equalized Distributed Receiver Front-End for UWB Direct Conversion Receivers,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007.

Vipul Jain, Sriramkumar Sundararaman, and Payam Heydari,  “A CMOS 22-29GHz Receiver Front-End for UWB Automotive Pulse-Radars,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007.

Deyi Pi, Byung-Kwan Chun, and Payam Heydari,  “A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007 [nominated for Best Paper Award].

Location: Juelich, Germany

Alex Nicolau, Furlong, J., A. Felch, J. Nageswaran, N. Dutt, A. Veidenbaum, A. Chandrashekar, and R. Granger,  “A Brain Derived Vision System Accelerated by FPGAs,” Proc. ParaFPGA: Parallel Computing with FPGA’s, September 4-7, 2007.

J. Furlong, A. Felch, J. Moorkanikara, N. Dutt, A. Nicolau, A. Veidenbaum, A. Chandrashekar, R. Granger, “Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements,” Proceedings of the 2007 Symposium on Parallel Computing with FPGA’s (ParaFPGA), Juelich, Germany, September 2007.

Date: Sept. 30 – Oct. 5, 2007
Location: Salzburg, Austria
Website: http://www.ida.liu.se/cnferences/codes

G. Stitt and F. Vahid, “Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), 2007, pp. 93-98

P. Chandraiah, R. Dömer: “Pointer Re-coding for Creating Definitive MPSoC Models”, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2007: pp. 33-38

Location: San Jose, CA
Website: http://ftg.lbl.gov/ppopp07/

Alex Nicolau, Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li, Sergey Kozhukhov, Utpal Banerjee, Alexander V. Veidenbaum, Constantine D. Polychronopoulos, “Tight analysis of the performance potential of thread speculation using spec CPU 2006”, Proc.  PPOPP 2007: 215-225, June 2007.

Location: Seattle, WA
Website: http://ics07.ac.upc.edu/

Alex Nicolau,  P.D’Alberto, “Adaptive Strassen’s Matrix Multiplication”, Proc. ACM  21st International Conference on Supercomputing, June 2007.