Towards Practical High-Level Synthesis from Large Behavioral Descriptions
|Speaker||Dr. Yuko Hara-Azumi
Nagoya University, Japan
|CECS Host||Nikil Dutt|
|Location||Donald Bren Hall (DBH) 3011|
|Date & Time||August 3, 2010
Lecture begins at 3:00PM
|Abstract||Due to the continuously increasing size and complexity of LSIs, the traditional Register-Transfer Level (RTL) design with Hardware Design Languages (HDLs) is approaching its limit on design productivity. High-level synthesis, which automatically synthesizes an RTL circuit from a behavioral description, is expected as a promising solution to improve design productivity. However, the LSI design has not been completely shifted from the traditional RTL design with HDLs to high-level synthesis yet since the quality of automatically synthesized RTL circuits through high-level synthesis can be inferior to that of human-designed ones, which is especially serious for large designs.
The goal of my work is to develop practical technologies of “high-level synthesis from large behavioral descriptions”. In this talk, first, one of my thesis works, which revealed some problems in current technologies of high-level synthesis, is briefly presented. Then, previous/ongoing works which tackle with the problems are presented.
Yuko Hara-Azumi received her Ph.D. degree in information science from Nagoya University in 2010. Currently she is a research fellow of the Japan Society for the Promotion and Science at Nagoya University. Also, she serves as a visiting researcher at Ritsumeikan University and University of California, Irvine. Her research interests include high-level synthesis and compiler techniques.