Advanced SoC Architectures for Multiple DRAMs
(Enabled by 3D Die Stacking)
|Dr. Sungjoo Yoo
|Professor Nikil Dutt
|Donald Bren Hall (DBH) 3011
|Date & Time
|November 17 , 2009
Refreshments at 1:30 pm, Lecture begins at 2:00 pm
|The performance of data-intensive applications is mostly determined by the bandwidth and latency of off-chip DRAM. In order to improve the bandwidth and latency characteristics, multiple memory-based solutions (enabled by 3D stacking of memory dies on top of LSI dies) are being actively investigated. With multiple DRAMs, we come to face new architectural problems, especially, in memory controllers and on-chip network. In this talk, we will discuss the architectural problems caused by multiple memories and present our solutions (request parallelizer, in-network reorder buffer, etc.) to address the problems. We will summarize this talk with some speculations on future SoC architectures with multiple memories.
Dr. Sungjoo Yoo received B.S., M.S., and Ph.D. at Seoul National University, Korea, in 1992, 1995, and 2000, respectively. He worked at TIMA laboratory, Grenoble, France from 2000 to 2004 and worked as principal engineer at System LSI Division, Samsung Electronics from 2004 to 2008. At Samsung, he led a team which developed AMBA3-based on-chip bus architectures for mobile SoCs, and low power design solutions such as dynamic voltage and frequency scaling (DVFS) algorithms and performed hardware/software co-optimization of solid state disk products. He joined POSTECH (Pohang university of science and technology) in August 2008. His current research interests include memory hierarchy and network-on-chip for many-core SoC, low power design based on runtime-distribution and temperature-aware DVFS, and power efficiency/performance/reliability improvement of solid state disk.