Automatic Design Space Exploration for Chip Multi-Processors

Speaker Dr. Cristina Silvano,
Politecnico di Milano
CECS Host Alex Veidenbaum
Location Donald Bren Hall (DBH) 3011
Date & Time June 17 , 2010
Refreshments at 10:30 am, Lecture begins at 11:00 am
Abstract Given the increasing complexity of Chip Multi-Processors, a wide range of architecture parameters (number of processors, processor issue width, L1 & L2 cache size, etc.) must be tuned to find the best trade-off in terms of multiple metrics (energy, delay, bandwidth, area, etc.). Multi-Objective exploration of the huge design space of next generation CMPs cannot be anymore based on intuition and past experience of the design architects. Automatic Design Space Exploration is necessary to support systematically the exploration and the quantitative comparison in terms of multiple objectives. This talk addresses these problems by presenting MULTICUBE Explorer, an open-source tool to support an automatic and fast optimization of configurable system-on-chip architectures towards a set of objective functions such as energy and delay. MULTICUBE Explorer provides a set of innovative sampling and optimization techniques to help finding the multi-objective Pareto points. Design of Experiments techniques are used to identify the experimentation plan where the set of tunable design parameters can vary. Response Surface Modeling techniques are used to obtain a response surface of the system behavior based on the set of data generated by DoE. MULTICUBE Explorer can also provide some support for run-time management of system resources.

She is an Associate Professor in Computer Engineering at Politecnico di Milano (Italy). Her primary research interests are in the area of Computer Architectures and Electronic Design Automation, with particular emphasis on design space exploration techniques and low- power design techniques for multi-processor systems-on-chip. She is co-author of more than seventy scientific papers on international journals and conferences, collecting one best paper award. She was co-author of the book: Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems, published by Kluwer Academic Publisher (2003). She also holds some international patents. She participated to a number of national and international research projects. She is currently the European Coordinator of the on-going project FP7-MULTICUBE-216693 “Multi-objective design space exploration of multi-processor SoC architectures for embedded multimedia applications” (Jan. 2008 – June 2010). >From 2010, she is also the Project Coordinator of the project FP7-2PARMA-248716 on “Parallel paradigms and run-time management techniques for many-core architectures.”