The Inevitable Use of High Level Synthesis in Complex SoC Designs
| Speaker | Dr. Benjamin Schaefer, NEC Research Lab, Japan |
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| CECS Host | Elaheh Bozorgzadeh | |||
| Location | Donald Bren Hall (DBH) 413 | |||
| Date & Time | June 11 , 2010 Lecture begins at 11:00 am (Lecture Cancelled) |
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| Abstract | ESL is becoming main stream when modeling complete SoCs in order to evaluate different architectural trade-offs and get some early performance estimates. These models are mainly described in SystemC. The central question that remains is if these models can ultimately be synthesized in order to further reduce the development cycle or if these models need to be manually described and integrated at the RT-level. This talk addresses how complete SoCs can be fully designed in C. | |||
| Biography |
Benjamin received his Ph.D from the University of Birmingham, UK in 2003 , where he investigated the acceleration of numerical intensive algorithms on reconfigurable computing platforms. He then moved to UCLA as a postdoctoral researcher working in the area of High Level synthesis and then moved to Seoul National University, Korea where he worked on thermal estimation and reduction issues in VLSI circuits. Since 2007 he is with NEC’s Central Research Laboratory in Japan, working on System and High Level Synthesis. |
