Bluespec: Why chip design can’t be left to EE’s

Speaker Professor Arvind
CSAIL (formerly LCS and AI Lab)
Massachusetts Institute of Technology
Location McDonnell Douglas Auditorium
Date & Time March 22, 2004
Refreshments at 2:30pm, Lecture begins at 3:00pm
Abstract Hundred million-gate ASICs are possible by the end of the decade. However, numerous problems related to process technology and design need to be solved before such large chips will become commonplace. Computer scientists are much better equipped to solve the new problems related to the design-in-the-large. Bluespec is a language/methodology that promotes correctness-by-construction. Its underlying execution model is based on atomic actions on state elements (such as flip-flops, registers, …), i.e., any legal behavior is explainable in terms of a sequence of atomic actions on the state. Expressiveness of Bluespec is achieved by keeping its static semantics orthogonal to its hardware execution semantics — the source program is turned into a flat interconnection of modules by “static elaboration” during the compile phase.

This talk will present Bluespec via examples and show some of the designs done so far.


Arvind is the Johnson Professor of Computer Science and Engineering at the Massachusetts Institute of Technology. His work at MIT on high-level specification, modeling, synthesis and verification of architectures and protocols using Term Rewriting Systems (TRSs) laid the foundations for Sandburst and more recently Bluespec Inc. Previously, he contributed to the development of dynamic dataflow architectures, and together with Dr R.S.Nikhil published the book “Implicit Parallel Programming in pH”. Arvind is an IEEE Fellow and was awarded the Charles Babbage Outstanding Scientist Award in 1994. He has received the Distinguished Alumni Awards from the Indian Institute of Technology, Kanpur, and the University of Minnesota.