Power Efficient and Fault Tolerant Circuits and Systems Using Commodity FPGA

Speaker Prof. Lei He
Electrical Engineering Department,
CECS Host Professor Eli Bozorgzadeh
Location Engineering Hall (EH) 2430
Date & Time October 9, 2009
Refreshments at 10:30am; Lecture begins at 11:00am
Abstract As devices become smaller, circuits and systems are more vulnerable to soft errors caused by radiation and other environmental upsets. Fault tolerance measured by mean time to failure (MTTF) is desired, especially if no extra area, power and delay and little change of the existing design flow are introduced. Using FPGA and internet router as a testbed, this talk first presents fault tolerance techniques applying (1) logic don’t care and path re-convergence (ROSE) and (2) in-place logic re-writing (IPR). Both increase MTTF by 2X with little or no overhead. Particularly, IPR does not change circuit placement and routing, and can be readily used with the existing industrial design flow. It also leads to a self evolution method to enhance fault tolerance for FPGA based circuits and systems. Finally, I will briefly discuss my ongoing research on cyber-physical systems involving renewal energy storage and environment/water monitoring.
Biography Dr. Lei He is an associate professor at electrical engineering department, UCLA, and was a faculty member at University of Wisconsin, Madison between 1999 and 2001. He also held visiting or consulting positions with Intel, Hewlett-Package, Cadence and Synopsys, was a technical advisory board member for Rio Design Automation, and Apache Design Solutions, and is a guest professor at Fudan University (China) and China National Laboratory for Optoelectronics.

His research interests include electronic design automation, VLSI circuits and systems, and cyber-physical systems. He has published one book and over 200 technical papers and has been a technical program committee member for a number of conferences including Design Automation Conference, International Conference on Computer-Aided Design, International Symposium on Low Power Electronics and Design, International Symposium on Field Programmable Gate Array, and International Symposium on Physical Design. Dr. He obtained Ph.D. degree in computer science from UCLA in 1999. He was granted National Science Foundation CAREER award in 2000, UCLA Chancellor’s faculty career development award in 2003, IBM Faculty Award in 2003, Northrop Grumman Excellence in Teaching award in 2005, best paper award at the 2006 International Symposium on Physical Design, and multiple best paper nominations at Design Automation Conference and International Conference on Computer-Aided Design.