Compiler-enabled Power-efficient Register File Protection
|Dr. Jongeun Lee
EECS, Ulsan National Institute of Science and Technology,Korea
|Donald Bren Hall (DBH) 3011
|Date & Time
|July 22, 2009
Refreshments at 10:30 am, Lecture begins at 11:00am
|Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing critical path of the processor, but also since it is one of the hottest blocks on the chip, and therefore adding any extra circuitry to it is not desirable. Software approaches would be ideal in this case, but previous approaches that are based on program duplication have very significant runtime overheads, and others based on instruction scheduling are only moderately effective due to local scope.
This talk will be about how compiler alone and in conjunction with microarchitecture can power-efficiently protect the RF. What we have observed is that a significant portion of the RF vulnerability is contributed by long lifetime variables. Protecting only these can result in power-efficient RF protection. Thus the task of the compiler is to identify program variables that have long lifetimes and protect them. Our experiments demonstrate pure compiler techniques can reduce the vulnerability of the RF by 33-37% on average and up to 66%, with a small (2%) runtime overhead. As compared to hardware protection mechanisms, compiler analysis can achieve the same level of protection but at up to 75% lesser RF energy consumption.
Jongeun Lee received a BS and an MS in Electrical Engineering and a PhD in Electrical Engineering and Computer Science all from Seoul National University. Previously he was with Samsung SoC R&D Center in Korea, and is currently a postdoctoral associate at Arizona State University, working with Dr. Aviral Shrivastava. He is joining Ulsan National Institute of Science and Technology, Korea, as an Assistant Professor of EECS. His research interests include configurable/reconfigurable processor architecture design, compilation for energy and reliability, and compilation for multicore processors and GPUs.