Embedded Microprocessor Cache and Translation Lookaside Buffer (TLB) Low Power Circuit Techniques for 90nm and Beyond

Speakers Jonathan R. Haigh and Michael W. Wilkerson
CECS Host Professor Alex Veidenbaum
Location McDonnell Douglas Auditorium
Date & Time Friday, February 6, 2004
Refreshments at 10:30am, Seminar begins at 11:00am
Abstract Optimizing power consumption is a primary goal in the design of embedded microprocessors even as the push for higher performance continues.  Managing the microprocessor’s power dissipation while still striving to push the design into GHz speeds provides a significant challenge.  As designs move to 90 nm and beyond, device scaling has reduced oxide thicknesses and V T to the point where standby leakage power is on the same order of magnitude as active power.  Today’s successful designs need to aggressively manage both active and standby currents.  A collection of methods to control both active and leakage power in Cache and Translation Lookaside Buffer (TLB) circuits, while minimizing the impact to performance, will be discussed.
Biography Jonathan R. Haigh: 
Jon is the lead L1 cache designer for the current generation of XScale products.  He began his EE career at GE in 1996 followed by the former Digital Semiconductor in 1998.  He joined Intel Corporation in 2000 and has been working on the XScale cache circuit design team since joining the company.  He received his B.S. degree in Electrical Engineering concentrating in VLSI design from the University of Cincinnati .

Michael W. Wilkerson: 
Mike received the B.S. and M.S. degrees in electrical engineering from the University of Florida in 1991 and 1997.  He was in the U.S. Navy from 1983 to 1996 and joined Intel Corporation in 1998.  He has worked in logic verification and VLSI circuit design for Itanium and XScale microprocessors while at Intel.  He most recently completed the physical design of the data path memory management unit, which includes a TLB structure, for a new XScale core.