High-Level Synthesis Using Partially-Programmable Resources for Yield Improvement
| Speaker | Dr. Yuko Hara-Azumi Ritsumeikan University, Japan |
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| CECS Host | Nikil Dutt | |||
| Location | Donald Bren Hall (DBH) 3011 | |||
| Date & Time | October 18, 2011 Refreshments at 2:30PM, Colloquium begins at 3:00PM |
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| Abstract | These years, there has been a considerable interest in practical techniques to improve the yield of LSIs at little sacrifice of performance and area. Recently, we presented a new concept device, called Partially-Programmable Circuit (PPC), which consists of conventional gates, LUTs, and wires, and enhances yield only by implicit logic redundancy (by partial reconfiguration of the LUTs) and redundant wires. In this talk, a novel high-level synthesis (HLS) approach using PPC-realized resources is presented. Considering reconfiguration of the resources after fabrication, our work aims at maximizing yield expectation. | |||
| Biography | Yuko Hara-Azumi received her Ph.D. degree in information science from Nagoya University in 2010. Currently she is a research fellow of the Japan Society for the Promotion of Science at Ritsumeikan University. Her research interests include system-level design methodology for embedded systems, especially high-level and logic synthesis, and task mapping technologies for many-core architectures. |