Recoding Infrastructure for SystemC (RISC)

Out-of-Order Parallel SystemC Simulation
on Many-Core Architectures

Principal Investigator: Rainer Dömer

The Recoding Infrastructure for SystemC (RISC) project addresses the advanced parallel simulation of embedded system models with hardware and software components. We focus on Transaction Level Models (TLM) described in the IEEE standard SystemC language and highly parallel applications, such as graphics processing pipelines (e.g. GPU subsystems) and multi-media codecs. As simulation host platform, the project targets modern multi- and many-core computer architectures, with a focus on the Intel(R) Many Integrated Core (MIC) architecture, in particular the Xeon(R) Phi(TM) Coprocessor.

The goal of the project is the efficient analysis and validation of IEEE SystemC design models through high-performance simulation with maximum parallelism for fast and accurate performance analysis and rapid design space exploration. This project encompasses the detailed study and research and development of (1) analysis, compilation and transformation tools for high-level SystemC design models, (2) advanced out-of-order parallel simulation algorithms for the SystemC language, and (3) efficient mapping of parallel threads onto a symmetric many-core platform.

Project Overview

At the center of the project is the research and development of a parallel simulation infrastructure for IEEE SystemC consisting of
  • a dedicated SystemC compiler with advanced static and dynamic model analysis for aggressive yet standard-compliant parallel simulation, and
  • a parallel SystemC simulator with out-of-order execution engine on many-core platforms.
Funding for this project has been provided by Intel Corporation.
The PI and project members are very thankful for this support.

This is an ongoing project. The material provided here is a work in progress and will change. Source code and documentation are provided as-is, without any guarantees.
Use RISC at your own risk!

Open Source Releases

The Recoding Infrastructure for SystemC (RISC) is an open-source framework for static and dynamic analysis and source-to-source transformations of IEEE SystemC models.
RISC is built on top of Accellera SystemC and the Rose compiler.
RISC provides a dedicated SystemC compiler and out-of-order parallel simulator, as well as model visualization and performance tuning tools. In addition, the RISC libraries offer access to the internal representation of SystemC models via documented application programming interfaces.
The RISC software and documentation are freely available below:

RISC API, Alpha Release V0.1.0: (2014-06-04) RISC Compiler and Simulator, Alpha Release V0.2.0: (2015-09-30) RISC Compiler and Simulator, Alpha Release V0.2.1: (2015-10-30) RISC Compiler and Simulator, Beta Release V0.3.0: (2016-09-30) RISC Compiler and Simulator, Release V0.4.0: (2017-07-31) RISC Compiler and Simulator, Release V0.4.2: (2018-06-15) RISC Compiler and Simulator, Release V0.5.0: (2018-09-30) Authors: (in alphabetical order):
  • Farah Arabi
  • Zhongqi Cheng
  • Rainer Doemer
  • Guantao Liu
  • Daniel Mendoza
  • Tim Schmidt
Center for Embedded and Cyber-Physical Systems (CECS),
University of California, Irvine

Project Publications

  • R. Dömer, Z. Cheng, D. Mendoza, A. Dingankar:
    "RISC: Recoding Infrastructure for SystemC, Open Source Framework for Parallel Simulation",
    Workshop on OpenSource EDA Technology at ICCAD, San Diego, California, November 2018.

10/02/18 R. Doemer (