Parallel SystemC Simulation
on Many-Core Architectures

Principal Investigator: Rainer Dömer
 
Overview
RISC
Publications
Overview

This project addresses the advanced parallel simulation of embedded system models with hardware and software components. We focus on classic Transaction Level Models (TLM) described in the IEEE standard SystemC language and highly parallel applications, such as graphics processing pipelines (e.g. GPU subsystems) and multi-media codecs. As simulation platform, the project targets modern multi- and many-core architectures, with a focus on the Intel(R) Many Integrated Core (MIC) architecture, namely the Xeon(R) Phi(TM) Coprocessor.

The goal of the project is the efficient validation of SystemC models through high-performance simulation with maximum parallelism for fast and accurate performance analysis and rapid design space exploration. This project contains the detailed study and research and development of (1) advanced out-of-order parallel simulation algorithms, (2) efficient mapping of parallel threads onto the available cores of a symmetric many-core platform, and (3) optimization for minimal inter-core communication overhead.
Project Overview

At the center of the project is the research and development of a SystemC-based simulation infrastructure consisting of
  • a dedicated SystemC compiler with advanced static and dynamic model analysis for aggressive yet standard-compliant parallel simulation, and
  • a parallel SystemC simulator with out-of-order execution engine on many-core platforms.
Acknowledgments:
Funding for this project has been provided by Intel Corporation.
The PI and project members are very thankful for this support.

Disclaimer:
This is an ongoing project. The material provided below is work-in-progress and will change. It is provided as-is, without any guarantees.
Use at your own risc! ;-)

RISC: Recoding Infrastructure for SystemC

An essential component for parallel SystemC simulation compliant with the standard language semantics is advanced compile-time analysis of the design model. Towards this end, this project delivers the Recoding Infrastructure for SystemC (RISC), an open-source framework and API for static model analysis and source-to-source transformations that is built on top of the ROSE compiler infrastructure.

RISC API, Alpha Release V0.1.0: (2014-06-04) RISC Compiler and Simulator, Alpha Release V0.2.0: (2015-09-30) RISC Compiler and Simulator, Alpha Release V0.2.1: (2015-10-30) RISC Compiler and Simulator, Beta Release V0.3.0: (2016-09-30) RISC Compiler and Simulator, Release V0.4.0: (2017-07-31) Authors: (in alphabetical order):
  • Zhongqi Cheng
  • Rainer Doemer
  • Guantao Liu
  • Tim Schmidt
Center for Embedded and Cyber-Physical Systems (CECS),
University of California, Irvine

Project Publications



07/31/17 R. Doemer (doemer@uci.edu).