News Announcements

April 29, 2008
"Hardware-Accelerated Formal Verification"
Distinguished Lecture
by Prof. Masahiro Fujita
     VLSI Design and Education Center
     University of Tokyo, Tokyo, Japan

A semi-formal verification technique, which performs a brute-force compiled simulation with a sophisticated search space pruning, has been proposed and shown to be competitive with the state-of-the-art SAT-based verification techniques, especially for complicated logics such as hardware having various arithmetic computation units. We have enhanced this technique by using an FPGA-based hardware accelerator...
View Abstract


April 2008
eNews Winter '08 Volume 8 Issue 2 Available
Vol8 Iss1

· Rainer Doemer wins NSF CAREER Award
· Minyoung Kim wins two awards at PhD forum
Download PDF





May 8, 2008
On-Chip Communication Architectures Book

On-Chip Communication ArchitecturesChancellor's Professor Nikil Dutt and PhD student Sudeep Pasricha have co-authored On-Chip Communication Architectures: System on Chip Interconnect.

On-Chip Communication Architectures is a definitive guide to on-chip communication architectures for emerging chip multi-processor systems and contains detailed analysis of all popular standards for on-chip communication.
View Details








Please e-mail your comments and suggestions to our webmaster
© Copyright 1997-2008 CECS-UCI. All rights reserved.