"Hardware-Accelerated Formal Verification"
Distinguished Lecture
by Prof. Masahiro Fujita
VLSI Design and Education Center
University of Tokyo, Tokyo, Japan
A semi-formal verification technique, which performs a brute-force compiled simulation with a sophisticated search space pruning, has been proposed and shown to be competitive with the state-of-the-art SAT-based verification techniques, especially for complicated logics such as hardware having various arithmetic computation units. We have enhanced this technique by using an FPGA-based hardware accelerator...
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eNews Winter '08 Volume 8 Issue 2 Available
· Rainer Doemer wins NSF CAREER Award
· Minyoung Kim wins two awards at PhD forum
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On-Chip Communication Architectures Book
 Chancellor's Professor Nikil Dutt and PhD student Sudeep Pasricha have co-authored On-Chip Communication Architectures: System on Chip Interconnect.
On-Chip Communication Architectures is a definitive guide to on-chip communication architectures for emerging chip multi-processor systems and contains detailed analysis of all popular standards for on-chip communication.
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