Date/Time: Thursday, August 1, 2013
Location: Engineering Hall 4106
Professor Ahmed Eltawil (Chair)
Professor Fadi Kurdahi
Professor Nikil Dutt
There are emerging needs to build energy efficient platforms to support co-operation between heterogeneous wireless networks. This necessitates building efficient frameworks for reconfigurable platforms that can support seamless reconfiguration among different wireless scenarios. Towards achieving that goal, this thesis addresses the problem of building energy efficient wireless architectures from two perspectives. First, we develop a high level framework that generates a reconfigurable MPSoC architecture from a library of heterogeneous processing resources that can be reconfigured to support various modes of operation. The framework proposes joint task and core mapping with system level floorplanning. With the objective of minimizing energy, we develop an analytical probabilistic model that considers static, dynamic, reconfiguration and communication energy components for multiple applications characterized by certain probabilities of execution. Fast and efficient heuristics have been developed that can achieve solutions very close to those obtained via optimal solvers, with several orders of magnitude speedup.
While, the first perspective focused on system level solutions, the second perspective focuses on the block level optimizations. It utilizes the fact that the use of embedded memory in its various forms and implementations for cellular base-stations and mobile handhelds has experienced unprecedented growth recently, significantly affecting area and power consumption metrics. Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories, which allows acceptable hardware errors to flow through the processing chain as a cost of considerable power savings. This thesis presents a model that captures the statistics of both channel noise and buffering memory failures. Furthermore, it introduces modified forward error correction (FEC) decoders that are aware of both the channel errors as well as the buffering memory errors. The decoding maximizes the likelihood of the received data based on the statics of the combined channel and buffering memory noise. The idea is applicable to three widely used FEC decoders; namely Viterbi, Turbo, and LDPC decoders. The modified decoders are able to preserve the system performance very close to the hardware error-free case with negligible area overhead in implementation.