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Cognitive Power Management and Error Resilient Algorithms for Memory Dominated Wireless Communication Systems

August 27, 2013 @ 3:00 pm - 4:00 pm PDT

Date/Time:  Friday, August 23, 2013

Location:  Engineering Hall 4106

Committee Members:
Ahmed Eltawil (Chair)
Fadi Kurdahi
A. Lee Swindlehurst


Advanced CMOS technology exhibits increasing variations in performance, power consumption and reliability parameters. These variations led to extensive overdesigning and increased power consumption to guarantee 100% reliable operation. However, with the continuous shrinking of device parameters, future semiconductor industry needs to shift from the assumption of 100% reliable computation to a fault-tolerant approach. Fortunately, many important application domains such as communication and multimedia are inherently error-aware, allowing a range of designs with a specified Quality of Service (QoS) to be generated for varying amounts of error in the system. Specifically, embedded memories in communication systems are perfect candidates for exploring error-aware designs, since the share of the System-on-Chips (SoCs) that is dedicated to memories has experienced an increasingly upwards trend exceeding more than 50% of the area of an SoCs for wireless standards such as Long-Term Evolution (LTE), Digital Video Broadcasting (DVB),  and Worldwide Interoperability for Microwave Access (WiMAX). Furthermore, a large portion of the memory is typically used for buffering data that already has a high level of redundancy (e.g. buffering memories in wireless chips). In the context of wireless communication systems, given that the incoming buffered data is already corrupted by time varying noise and interference, there is no need to store the data samples in memories that are error free, 100% of the time. Rather, Voltage over-scaling (VoS) techniques can be adopted as an efficient means to achieve energy efficient systems via trading off reliability versus power.  However, reducing the supply voltage of buffering memory through VoS results in spatially uniform random errors which in turn corrupt the stored data in the buffering memories and increase the noise floor.

In this thesis, the predominance of embedded memories in current and emerging wireless transceivers is utilized as a means to save power via channel state aware voltage scaling. While the wireless channel is a stochastic channel where the designer has little control on its variables, embedded memories are considered as an extension of the channel where the designer can control its quality via VoS. The thesis presents a unified statistical model that captures both errors in embedded memories due to voltage over-scaling and wireless channel impairments into a single Gaussian distribution model that represents a combination of communication channel noise and hardware noise. The proposed model is used to investigate different cognitive power management policies that capture the performance of the system as a function of both channel and hardware dynamics, thus creating a much richer design space of power, performance and reliability. Furthermore, based on that model, error-resilient algorithm for Viterbi decoder, multiple input multiple output (MIMO) detector and memory-based computation are presented.


August 27, 2013
3:00 pm - 4:00 pm PDT
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