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Out-of-order Parallel Discrete Event Simulation for Electronic System-Level Design

June 19, 2013 @ 3:00 pm - 4:00 pm PDT

Date/Time: Thursday, June 6th, 10:00 a.m. – 11:00 a.m.
Location: CECS Conference Room, Engineering Hall 3206

Committee Members:
Rainer Dömer (Chair)
Daniel Gajski
Brian Demsky

The large size and complexity of the modern embedded systems poses great challenges to design and validation. At the so called electronic system level (ESL), designers start with a specification model of the system and follow a systematic top-down design approach to refine the model to different abstraction levels by adding step-by-step implementation details. ESL models are usually written in C-based System-level Description Languages (SLDLs), and contain the essential features such as clear structure and hierarchy, separate computation and communication, and explicit parallelism. The validation of ESL models typically relies on simulation. Fast yet accurate simulation is highly desirable for efficient and effective system design.

The out-of-order parallel discrete event simulation (OoO PDES) is a novel approach for efficient validation of system-level designs by exploiting the parallel capabilities of todays multi-core PCs for system level description languages. OoO PDES breaks the global simulation-cycle barrier of traditional DE simulation by localizing the simulation time into each thread, carefully delivering notified events, and handling a dynamic management of simulation sets. Potential conflicts caused by parallel accesses to shared variables and out-of-order thread scheduling are prevented by an advanced predictive static model analyzer in the compiler. As such, OoO PDES allows the simulator to effectively exploit the parallel processing capability of the multicore system to achieve fast speed simulation without loss of simulation and timing accuracy.

We perform simulation experiments on both highly parallel benchmark examples and real- world embedded applications including a JPEG image encoder, an edge detector, a MP3 audio decoder, a H.264 video decoder, and a H.264 video encoder. Experimental results show that our approach can achieve significant simulation speedup on multicore simulation hosts with negligible compilation cost.

Based on our parallel simulation infrastructure, we then propose a tool flow for dynamic race condition detection to increase the observability for parallel ESL model development. It helps the designer to quickly narrow down the debugging targets in faulty ESL models with par- allelism. This approach helps to reveals a number of risky race conditions in our in- house embedded multi-media application models and enabled us to safely eliminate these hazards. Our experimental results also show very little overhead for race condition diagnosis during compilation and simulation.

Overall, our work provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development. It helps the embedded system designers to build better products in shorter time-to-market.


June 19, 2013
3:00 pm - 4:00 pm PDT
Event Category: