Technical Reports

Q. Xie, D. D. Gajski, "Parity Checker Implementations in SpecC,” TR 02-06, January 27, 2002. download pdf

 

D. D. Gajski, L. Cai, “Variable Mapping of System Level Design," TR 02-32, October 8, 2002. download pdf

 

A. Gerstaluer, “SpecC Modeling Guidelines,” TR 02-16, April 12, 2002. download pdf

 

H. Yu, D. D. Gajski, “Datapath Synthesis for a 16-Bit Microprocessor,” TR 02-05, January 22, 2002. download pdf

 

D. D. Gajski, L. Cai, “Grouping-Based Architecture Exploration of System-Level Design," TR 02-31, August 16, 2002. download pdf

 

J. Peng, L. Cai, A. Gerstlauer, D. D. Gajski, “Interactive System Design Flow,” TR 02-15, April 15, 2002. download pdf

 

P. Mishra, N. Dutt, “Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV,” TR 02-26, September 13, 2002. download pdf

 

W. Mueller, R. Doemer, A. Gerstlauer, “The Formal Execution Semantics of SpecC,” TR 02-04, January 11, 2002. download pdf

 

S. Gupta, N. Savoiu, N. Dutt, R. Gupta, A. Nicolau, “Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis," TR 02-29, October 1, 2002. download pdf

 

J. Peng, S. Abdi, D. D. Gajski, “Automatic Model Refinement for Fast Architecture Exploration,” TR 02-14, April 1, 2002. download pdf

 

A. Ghosh, T. Givargis, “Analytical Design Space Exploration of Caches for Embedded Systems,” TR 02-27, September 11, 2002. download pdf

 

R. Jejurikar, R. Gupta, “Efficiency and Optimality of Static Slowdown for Periodic Tasks in Real-Time Embedded Systems,” TR 02-03, March 19, 2002. download pdf

 

S. Abdi, J. Peng, R. Doemer, D. Shin, A. Gerstlauer, A. Gluhak, L. Cai, Q. Xie, H. Yu, P. Zhang, D. D. Gajski, “SCE Environment – Tutorial," TR 02-28, September 24, 2002. download pdf

 

D. Shin, D. D. Gajski, “Interface Synthesis from Protocol Specification,” TR 02-13, April 12, 2002. download pdf