Professor Givargis’s Research

Dr. Givargis conducts research in the general area of embedded systems with an emphasis on system software, advanced compilation for targeted applications, computational storage devices, accelerators and high dimensional computing.


  • P13. T. Givargis. Storage Device Embedded Strand Architecture. United States Patent, 10,558,567, February 11, 2020.
  • P12. T. Givargis. Tree Structure Serialization and Deserialization Systems and Methods. United States Patent, 10,216,627, February 26, 2019.
  • P11. T. Givargis, R. Sadri. Methods for Optimizing Data Movement in Solid State Devices. United States Patent, 8,612,719, December 2013.
  • P10. T. Givargis. Systems and Methods for Managing Key-Value Stores. United States Patent, 8,612,402, December 2013.
  • P9. A. Nacul, T. Givargis. Phantom Serializing Compiler and Method of Operation of Same. United States Patent, 7,886,283, February 2011.
  • P8. J. Addink, S. Addink, T. Givargis. Methods and Apparatus for Using Water Use Signatures and Water Pressure in Improving Water Use Efficiency. United States Patent 7,330,796, February 2008.
  • P7. J. Addink, S. Addink, T. Givargis. Methods and Apparatus for Using Water use Signatures in Improving Water use Efficiency. United States Patent 6,963,808, November 2005.
  • P6. J. Addink, T. Givargis. Interactive Irrigation System. United States Patent 6,950,728, September 2005.
  • P5. J. Addink, K. Buhler, T. Givargis. Modifying Irrigation Schedules of Existing Irrigation Controllers. United States Patent 6,892,114, May 2005.
  • P4. J. Henkel, T. Givargis, F. Vahid. Method for Core-Based System-Level Power Modeling using Object-Oriented Techniques. United States Patent 6,865,526, March 2005.
  • P3. K. Buhler, T. Givargis. Two Tire Irrigation Valve Controller. United States Patent 6,812,826, November 2004.
  • P2. J. Addink, T. Givargis. Detecting Weather Sensor Malfunctions. United States Patent 6,714,134, March 2004.
  • P1. J. Addink, K. Buhler, T. Givargis. Irrigation Accumulation Controller. United States Patent 6,298,285, October 2001.

Selected Projects


Cyber-Physical Systems (CPS) have an extraordinary potential to change industry, the economy and our lifestyles, but they also present an enormous design-science challenge, as CPSs require integration of different types of knowledge from many different disciplines.  The overall objective of DesignSciCPS is to create a general CPS design-science that makes design of every CPS simpler, faster and more dependable, while at the same time reducing the cost and the required expertise level.  DesignSciCPS aims to extend the well-understood methodology for embedded system design with new models and design-space exploration techniques, covering the cyber and the physical part of the systems.

Synthesis of Time-Controllable Digital Mockups of Physical Systems

This project creates digital mockups that are accurate and fast by using modern field-programmable gate array (FPGA) chips. It is the first to develop automated synthesis techniques for converting
numerous differential equations, forming the core of physical system models, into circuits on FPGAs. The project evaluates various differential equation solution techniques for FPGA suitability, and
develops an interconnected processing element target architecture. The project supports real-time execution and time-controllable execution via lightweight kernel definition on those processing elements. It develops a system synthesis approach to explore the solution space for a given physical model and FPGA device. The project includes expansion of existing embedded systems educational material, and trains numerous graduate and undergraduate students. Ultimately, the project will catalyze use of digital mockups and hence lead to better embedded computers.

XGRID: A Many-Core Embedded Platform with a Programmable Communication Fabric

This project explores an FPGA-like communication fabric for a many-core embedded compute platform. This platform allows a compiler-driven custom communication topology to be statically configured. Software running on the cores use buffered and synchronized message passing for communication.