IEEE Transactions on VLSI

D. Shin, A. Gerstlauer, R. Doemer, D. Gajski, “An Interactive Design Environment for C-based High-level Synthesis of RTL Processors,” IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 4, pp. 466-475, April 2008.

P. Heydari and R. Mohanavelu, “Design of Ultra High-Speed Low-Voltage CMOS CML buffers and Latches,” to appear in IEEE Trans. on VLSI Systems2004.
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P. Heydari and M. Pedram, “Ground Bounce in Digital VLSI Circuits,” IEEE Trans. on VLSI Systems, Vol. 11, No. 2, pp 180-193, April 2003.
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J. Zhu, D. D. Gajski, ” An Ultra-Fast Instruction Set Simulator,” IEEE Transactions on VLSI, Vol. 10, No. 3, June 2002, pp 363-373

S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, “FABSYN: Floorplan-aware Bus Architecture Synthesis,” IEEE Trans. on VLSI, Vol 14, No. 3, March 2006, pp 241-253.
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